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Incremental Multi Block Concurrent Design Optimization for Timing Closure

IP.com Disclosure Number: IPCOM000241509D
Publication Date: 2015-May-07
Document File: 4 page(s) / 200K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a methodology framework that enables targeted design optimization in parent context with multiple child blocks simultaneously exposed for optimization. The main proposal is to perform parent-level timing optimization in an incremental manner in which the entire timing arc is exposed at same time and is available for design changes and/or optimizations.

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Incremental Multi Block Concurrent Design Optimization for Timing Closure

Incremental Synthesis/placement/routing is a state-of-the-art design optimization technique used in targeted design optimization for big and complex design blocks. It helps in turnaround time (TAT) improvement and ensures better design stability. In current Incremental methodology, one specific design block is taken up at a time for targeted timing closure and other design optimization needs. This approach eventually leads to design closure; however, if the parent design has many boundary path-related violations, then this approach can be error prone and/or slow to converge because of timing assertion related inaccuracies at block interface and other issues.

Alternative methodologies are needed to efficiently solve this problem.

Figure 1 illustrates a parent level design in which Child-A and Child-B have timing violations as seen at parent level timing analysis. This needs to be fixed overall. Current state-of-art timing analysis would generate timing constraints (asserts) for child-A and child-B based on slack apportionment concept (different flavor). Multiple churns of design optimization (global or incremental synthesis/routing for individual child blocks/parent level buffering/wire-opt) followed by block and parent level loop-back timing take down are necessary for successful design closure. TAT issues, possible anomaly in asserts generation, multiple hand shaking between stakeholders are key issues with state-of-art.

Figure 1: Problem: Child-A level optimization does not have any visibility or influence

over child-B level or parent level optimization scope - multiple individual attempts and timing constraint updates are used

The novel contribution is a methodology framework that enables targeted design optimization in parent context with multiple child blocks simultaneously exposed for optimization. The main proposal is to perform parent-level timing optimization in an incremental manner in which the entire timing arc is exposed at same time and is available for design changes and/or opti...