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A method to do pin planning for efficient closure of electromigration issues in a chip

IP.com Disclosure Number: IPCOM000241513D
Publication Date: 2015-May-08
Document File: 6 page(s) / 211K

Publishing Venue

The IP.com Prior Art Database

Abstract

As technology is shrinking, more and more devices are being packed into the same VLSI chip and the number of transistors in a chip is exceeding several billion. The design complexity in terms of power, performance, area and time to market are the driving factors for EDA tools. Improved efficiency in handling large designs is critical to be able to meet the goals and specifications.

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A method to do pin planning for efficient closure of electromigration issues in a chip

As technology is shrinking, more and more devices are being packed into the same VLSI chip and the number of transistors in a chip is exceeding several billion. The design complexity in terms of power, performance, area and time to market are the driving factors for EDA tools. Improved efficiency in handling large designs is critical to be able to meet the goals and specifications.

Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of this effect increases.

This is one of the major reliability issues seen in devices and chips in deep micron technologies. This is getting more significant since the wire dimensions for the backend of the line metal is decreasing and the current densities are increasing. Voltage scaling is not keeping up with this hence risk of electromigration is increasing.

In the design of hierarchical chips, a macro or a physical partition often drives significant cap loads in the parent level of hierarchy causing better drivers and wires to be placed at the output of the macros at the pin boundaries. Often the actual cap load is given to the designer much later in the design due to dependencies at the parent level. Hence it is difficult to design the correct size of drivers at the outputs early. In the late design cycle there is not enough room to get the correct size drivers due to placement restrictions from other logic.

This method attempts to solve this problem by early planning of pins and spacing them such that better drivers can be placed at the boundaries and adequate space is reserved for them.

Describe known solutions to this problem (if any).

In the current methodology, the pin assignment is done either top down based on the connectivity of the parent or bottoms up based on the cell placements inside the macro.

The drivers for the pins are placed based on timing and connectivity.

When there is an electromigration violation, the cap load on the net is reduced by buffering or by increasing the width of the wires.

Disadvantages of the existing solutions

In order to fix the electromigration fails on pins, the connecting wires need to be widened and the drivers need to be in very close proximity to the pins. These fixes are typically identified late in the design cycle. If there are several failing pins placed close to each other, there is little room to connect to wide wires or move the drivers close to the pins.

Also, if the existing drivers are downsized for decreasing current density, it will lead to timing degradation

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