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OSAT Methods for Manufacture of Fine Pitch Solder Joints

IP.com Disclosure Number: IPCOM000241567D
Publication Date: 2015-May-12
Document File: 5 page(s) / 210K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are multiple methods to selectively embed solder within ultra-fine pitch voids in pre-applied underfill. Once filled with solder, these voids provide bumps that are used to create universal solder joints, which provide electrical connections to copper (Cu) pillars without the use of high accuracy alignment and bonding processes.

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This is the abbreviated version, containing approximately 40% of the total text.

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OSAT Methods for Manufacture of Fine Pitch Solder Joints

This disclosure provides multiple methods to selectively embed solder within ultra -fine pitch voids in pre-applied underfill. Once filled with solder, these voids provide bumps that are used to create universal solder joints, which provide electrical connections to copper (Cu) pillars without the use of high accuracy alignment and bonding processes .

Avoidance of these processes reduces assembly time and cost .

The disclosed processing methods offer advantages over conventional processes . The advantages of universal solder joints apply. Typical Chip Package Interaction (CPI) stresses formed during boding operations are minimized by applying and curing the underfill before assembly. The direct application of underfill to the wafer enables the use of increased filler loading, which would otherwise hinder underfill spreading. Increased loading in the underfill improve CPI reliability and improve heat transfer near heat producing integrated circuits (ICs). This method allows a minimum amount and thickness of solder to be used to create electrical connections , thus helping to mitigate electromigration issues. This method also supports the use of a wide variety of injection molded soldering (IMS) solders, which include ternary or quaternary compositions, which would be otherwise difficult to incorporate. The methods provided here enable wave soldering and IMS to embed solder on a supportive interface , which improves solder adhesion to underfill (UF) while creating an encapsulating barrier around the solder joint. Additional methods allow solder embedding using photolithographic processing techniques rather than necessitating the use of IMS techniques.

Implementation #1: Photolithographic Processing (Not used to define solder placement)

Primary: Tri-Layer Seed Layer (Note: Figures 1 and 2 also represent the starting points for the Secondary Steps in Implementation #1.)

Figure 1: Starting point -- A conductive terminal (2) is imbedded within a non-conductive layer (1). A dielectric film (3) is placed over the other layers.

Figure 2: An opening (4) is formed the dielectric film (3) which extends to the conductive terminal (2). The opening can be created using an excimer laser.

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Additional embodiments include other methods for opening the dielectric layer , using a photosensitive polymer with photolithography to create an opening in the dielectric .

Figure 3: Apply barrier (5), adhesive (6), and conductive (7) layers across the surface of the workpiece. The barrier layer can include materials such as TaN, Co, CoMn Ti, TiW, or Ru. The adhesive layer can include materials such as CuCr, NiV, Ni. The conductive layer can include materials such as Cu, CuMn, and Au. These layers can be applied using techniques such as plasma sputtering, evaporation, atomic layer deposition (ALD), and chemical vapor deposition (CVD).

Figure 4: Planarize the workpiece to remove exposed port...