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Post-placement Port Adjustment in Hierarchical Designs

IP.com Disclosure Number: IPCOM000241574D
Publication Date: 2015-May-13
Document File: 4 page(s) / 748K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention provides a method to help perform port assignment optimization jointly with both block internal and top level connection considered simultaneously.The optimization is based on the existing block placement result, and will no need to rerun placement for top or this block anymore. The invention is achieved by the following way: Consider the “first block_reg->port” path and “port->top_reg” path as a virtual hierarchy and fix the reg placement location and unfix ports locations of block, then optimize port location to achieve better global congestion and timing result using maximum weight matching algorithm of bipartite graph. With this method, the assignment of ports is optimized considering both block and top environment jointly instead of only one of them independently. As a result, resources near the port area can be leveraged more efficiently on the whole chip scale.

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Post

Post-

--placement Port Adjustment in Hierarchical Designs

placement Port Adjustment in Hierarchical Designs

As technology goes into deep sub-microns, chips become more and more complex. It becomes impossible to design a chip in a flattened way. As a result, hierarchy design is adopted, which means top level and block level are processed separately.

A typical custom design flow is shown in Fig.1, after design entry and initialize, top level will do floorplanning first. During top floorplanning, individual blocks are sized and shaped. After that, ports are assigned for eachblock. A good assignment will facilitate connections/communications from/to external components (blocks or IPs) with the objective of minimizing the wire length and delay. Port assignment can be taken as the protocol for top and block level works in hierarchical design.

Design Entry

Design Entry

Initialize Design

Initialize Design

Top floorplanning and Block sizing/port assignment

Top floorplanning and Block sizing/port assignment

Block placement

Top placement

Block placement

Top placement

No

Congestion accepted

Congestion accepted

No

No

Congestion accepted

Congestion accepted

No

Yes

Yes

Top and block joint optimization

Continue later steps

Continue later steps

Fig 1. Typical custom design flow Fig 2. Updated design flow

Then, placement is performed and iteratively improved separately, which makes top and block designers focus on their respective contexts at one time. With the assigned port location, block will do placement and iterate to achieve better congestion and timing results. When all blocks are doing the internal placement optimization, top level designer will run its own placement iterations. Clocking, routing and timing fix will also continue in such a parallelmanner when top and block placement are both acceptable to close the chip design.

As mentioned before, in hierarchical flow, port assignment is treated as the protocol between the cell inside block and cell on top level, which connects both block level and top level. In the ideal situation, the port assignments should be optimized for both block internal connection and top level. But in current flow, there is always a gap when

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doing placement separately on top and block level, which means: 1) The port assignment and boundary congestion optimization are operated independently for top and clock placement. This problem is caused by hierarchical placement itself, which means even a perfect port assignment before placement can also suffer from this disadvantage.

2) As long as hierarchical methodology is adopted, this disadvantage will not be prevented. Because in separate placement, the legalization step will always bring in some random placement in a local area. That means top and block level cells related to the ports will be handled first to meet the placement closure and then optimize timing and congestion on their own side. It cannot guarantee that these cells are placed in a...