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Area-Efficient Squaring Circuit with Full-Precision and Approximate Options

IP.com Disclosure Number: IPCOM000241607D
Publication Date: 2015-May-15
Document File: 5 page(s) / 146K

Publishing Venue

The IP.com Prior Art Database

Abstract

An area-efficient squaring circuit is proposed with full-precision and approximate options. The proposed squaring circuit consists of three blocks. First, a partial product generation block is to generate the partial products and the compensation if the squaring circuit works in approximate mode. Second, the compression block compresses the partial products and the compensation to two 2n-bit partial products. Third, the final addition block adds the two partial products and generates the final product for the squaring circuit.

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Area-Efficient Squaring Circuit with Full-Precision and Approximate Options

ABSTRACT

      An area-efficient squaring circuit is proposed with full-precision and approximate options. The proposed squaring circuit consists of three blocks. First, a partial product generation block is to generate the partial products and the compensation if the squaring circuit works in approximate mode. Second, the compression block compresses the partial products and the compensation to two 2n-bit partial products. Third, the final addition block adds the two partial products and generates the final product for the squaring circuit.

1.       INTRODCUTION AND MOTIVATION

      Squaring circuits have numerous applications such as microcontrollers, DSP and graphic processors. For some applications without any error allowed, a full-precision product is required from a squaring circuit. On the other hand, for some applications with inherent error resilience, a small error of a squaring circuit’s product is allowed. Approximate squaring circuits are applied for those applications with inherent error resilience to trade off accuracy for the benefit of significant reduction of area and energy consumption. Therefore, the squaring circuits which enable both full-precision squaring operation and approximate squaring operation are needed so that both types of applications can be applied.

      To enable both full-precision and approximate squaring operations, a single and area-efficient squaring circuit with full-precision and approximate options are needed, instead of one full-precision squaring circuit and one approximate squaring circuit implemented separately on the same chip. To design a squaring circuit with both full-precision and approximate options, an efficient partial product generation scheme needs to be come up, with different compensations targeting for minimizing different error metrics, such as average error, mean squared error, maximum error and absolute average error. To compress the partial products and the compensation if the squaring circuit works in approximate mode, an efficient compression scheme is needed to compress the number of partial products to two for final addition.

2.       PROPOSED AREA-EFFICIENT SQUARING CIRCUIT

As shown in Fig. 1, there are three inputs to the squaring circuit. First, A is an n-bit number. Second, mode is a 1-bit binary number used to select between full-precision mode and approximate mode. If mode is 0, the squaring circuit operates in full-precision mode. Otherwise, the squaring circuit works in approximate mode. Third, sel is a 2-bit number used to select an optimal compensation value if the squaring circuit operates in approximate mode. More details of sel are described in section 2.1 and section 2.2. The output P is a 2n-bit product of the squaring circuit.

Partial product generation block, compression block and final addition block are the three components of the proposed squaring circuit. The partial produc...