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Glitch Free Clock Multiplexer Circuit

IP.com Disclosure Number: IPCOM000241609D
Publication Date: 2015-May-15
Document File: 3 page(s) / 917K

Publishing Venue

The IP.com Prior Art Database

Abstract

When dynamically selecting clock from multiple clocks, in order to get the glitch free switching, it is often using some complex finite state machine (FSM) implementation, especially for asynchronous clock selecting. In this paper we present a simple way to eliminate the glitch when dynamically changing clock sources using a clock multiplexer with handshake scheme

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Glitch Free Clock Multiplexer Circuit

Abstract

When dynamically selecting clock from multiple clocks, in order to get the glitch free switching, it is often using some complex finite state machine (FSM) implementation, especially for asynchronous clock selecting.  In this paper we present a simple way to eliminate the glitch when dynamically changing clock sources using a clock multiplexer with handshake scheme.

Introduction

When clock sources are dynamical changing, we use an “add” gate and asynchronous handshake signal to control the clock switching.  Firstly enable  the “add” gate to gate the clock out by old clock, and then switching the clock from old clock to new clock, at last disable the “add” gate to let the new clock pass through.

Design and Implementation

Figure 1 shows the structure of the circuit of glitch free clock multiplexer.  There are five main components:
(1) two MUXes: MUX1,MUX2;

(2) FF1 & FF2 and a comparison circuit to fulfill clocks selection signals update.

(3) FF3&FF4&FF5 to detect the handshake signal changes.

(4) A handshake signal generation component.

(5) ADD1 as a gate cell to gate clock out or not. 

When clock select signals are changing such as from clock 0 to clock 1, the MUX1 doesn’t change because the MUX1 select signals are gating by the handshake signal “clock_sel_mism”. But the MUX2’s out clock will update to be clock 1 immediately.  The components (2) will detect the “clock_sel” change in clock 0 domain, and then set a handshake signal “clock_sel_mism”. And at the same time “add1” will gate the target clock...