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An efficient methodology to achieve the best possible wiring design compromise to achieve the targeted specifications applied to large silicon devices arrays.

IP.com Disclosure Number: IPCOM000241696D
Publication Date: 2015-May-22
Document File: 4 page(s) / 129K

Publishing Venue

The IP.com Prior Art Database

Abstract

Abstract Disclosed is a new design methodology applicable for layout optimization of large silicon devices such as power amplifiers or switches. The main features and building blocks are: - the addition in a standard PDK of all the necessary procedures to generate a hierarchical programmable cell (pcell) that offers the user to rapidly generate design rule checker (DRC) & layout versus schematic (LVS) clean transistor arrays suitable to find the optimal wiring tradeoff. - A large number of layout variations can be rapidly explored and screened at a high level ( trends versus detailed absolute value) , with the intent to keep only a few layouts that are best aligned to the product constraints. - The few options that are left can then be simulated in details, using full parasitic extraction to refine the results, and achieve an optimum layout providing the best constraints tradeoff or the optimal manufacturability This approach lends itself to the following advantages when compared with the current state-of-the-art : - a faster convergence to achieve the optimal solution - a gain in productivity & guidance provided to the designer to choose the relevant process/kit parameters to design efficiently - allow the selected layout, once defined to be further optimized using process tuning or manufacturing changes without the necessity to redesign from scratch.

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An efficient methodology to achieve the best possible wiring design compromise to achieve the targeted specifications applied to large silicon devices arrays.

Current radio-frequency (RF), high power, analog and mixed signal product designs require, to successfully impact the market, the designer to understand and perform the necessary technology tradeoffs [1]. An increased level of automation is used to achieve the correct balance between technical specifications, economical constraints and compliance to industrial standards .

    This task is most difficult for front-end RF applications, such as power amplifiers (PAs), [2,3] antenna switches, high power and fast input-output (I/O) devices, that require to achieve the proper layout that meet all electrical, thermal, reliability.. etc requirements of very large devices ( or array of devices ) built by

wiring together elementary ( small ) unit elements offered in standard process design kits (PDKs) .

Today, one of the limiting aspects of this activity is the lack of automation that

would allow designers to choose the appropriate wiring approach. This proposal allows the designers to design in their standard framework several wiring options compliant with the technology rules, fully model these resulting large and complex structures, in an attempt to achieve an optimal solution within their limited development schedule.

    Disclosed is a new design methodology applicable for layout optimization of large silicon devices such as power amplifiers or switches. The main features and building blocks are:

- the addition in a standard PDK of all the necessary procedures to generate a hierarchical programmable cell (pcell) that offers the user to rapidly generate design rule checker (DRC) & layout versus schematic (LVS) clean transistor arrays suitable to find the optimal wiring tradeoff.

- A large number of layout variations can be rapidly explored and screened at a high level ( trends versus detailed absolute value) , with the intent to keep

only a few layouts that are best aligned to the product constraints.

  - The few options that are left can then be simulated in details, using full parasitic extraction to refine the results, and achieve an optimum layout providing the best constraints tradeoff or the optimal manufacturability
This approach lends itself to the following advantages when compared with the current state-of-the-art :
- a faster convergence to achieve the optimal solution
- a gain in productivity & guidance provided to the designer to choose the relevant process/kit parameters to design efficiently
- allow the selected layout, once defined to be further optimized using process tuning or manufacturing changes without the necessity to redesign from scratch.

    The best way to illustrate the new approach is through the description of the regular design flow used to develop large analog or RF devices . At product level, applications targeted are broad, ranging from high power RF transceivers,...