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Method and System for Forming Gate to CA Airgap Spacer for Reducing Capacitance Between Gate and CA

IP.com Disclosure Number: IPCOM000241714D
Publication Date: 2015-May-26
Document File: 3 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and system for forming Gate to CA airgap spacer. The airgap spacer at the gate side walls reduces capacitance between the gate and CA.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 3

Method and System for Forming Gate to CA Airgap Spacer for Reducing Capacitance Between Gate and CA

A method and system is disclosed for forming gate to CA airgap spacer . The airgap spacer at the gate side walls reduces capacitance between the gate and CA .

The process begins with the state-of-art flow post liner as shown in fig. 1.

Fig. 1

Thereafter, SAC contacts are formed as shown in fig. 2.

Fig. 2

In the next step, TiN/W is deposited and polished off as shown in fig . 3.

Fig. 3

Thereafter, the contacts are recessed as shown in fig. 4

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Page 02 of 3

Fig. 4

The contacts are recessed similar to gate recess with same material being used . Moving to next step, low-k spacers are recessed. SiOCN can be recessed selectively to SAC cap and metal as shown in fig. 5.

Fig. 5

Subsequently, as shown in fig. 6, PECVD nitride is depped to pinch -off the spacer region and to create air-gap.

Fig. 6

Fig. 7 illustrates a final structure where nitride is cleared off from top of the contact and thereafter, further wiring is done.

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Page 03 of 3

Fig. 7

The method and system provides a structure to reduce capacitance between gate and CA by forming an airgap spacer at the gate side walls.

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