Browse Prior Art Database

On-Chip Inductors

IP.com Disclosure Number: IPCOM000241727D
Publication Date: 2015-May-26
Document File: 5 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an inductor structure with high u Ferrite material on the top and bottom to prevent magnetic field loss and lower quality factor and improve performance at chip level. The solution includes a process for fabrication that is compatible with standard Complimentary Metal-Oxide Semiconductor (CMOS) technology flow.

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On-Chip Inductors

On-chip inductors so far are "open" on the top and bottom, resulting in a magnetic field loss and lower quality factor. The current on-chip inductor also impacts surrounding circuits and degrades performance at chip level.

Figure 1: Current structure

Known solutions do not address the problems described.

The novel solution is an inductor structure with high u Ferrite material on the top and bottom to prevent the above issues. The solution includes a process for fabrication that is compatible with standard Complimentary Metal-Oxide Semiconductor (CMOS) technology flow.

Figure 2: Starting at Back End of Line (BEOL) process step, deposit high u ferrite material (e.g., nickel-zinc (NiZn)

Figure 3: Deposit dielectric1 (nitride or oxide)

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Figure 4: Patterning and etch

Figure 5: Dielectric2 deposition and Chemical Mechanical Planarization (CMP)

Figure 6: BEOL Patterning, etching stop at dielectric1

Figure 7: BEOL metal deposition and CMP

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Figure 8: Dielectric1 deposition

Figure 9: Ferrite material deposition

Figure 10: Litho

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Figure 11: Etching

Figure 12: Remove resist and dielectric2 deposition

Figure 13: For Vx and wiring out

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