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Method and Apparatus for Safe-Stating, Isolation Enabling, and Crowbar Current Reduction of a multi-Voltage Domain, Power Sequence Independent SOC

IP.com Disclosure Number: IPCOM000241895D
Publication Date: 2015-Jun-05
Document File: 3 page(s) / 189K

Publishing Venue

The IP.com Prior Art Database

Abstract

Today’s SOC’s are required to be power sequence independent. In such SOC’s, IP level safe-stating is handled by safe-stating level shifters at various boundaries where IP designers use various type of cells to detect supplies and safe-state level shifter’s input and output. Many power domain signal crossing errors are found in the last stages of SOC design or in silicon, which results in heavy cost penalties either in terms of time to market or silicon respin. A standard method is needed to indentify power domain crossings and deploy voltage detectors to generate safe-stating signals for level shifters at these crossings to keep inputs and outputs at known safe states. In this paper we explain, in nut shell, important aspects of a framework that allows achieving this objective.

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Method and Apparatus for Safe-Stating, Isolation Enabling, and Crowbar Current Reduction of a multi-Voltage Domain, Power Sequence Independent SOC

                                                                                                         

Abstract 

Today’s SOC’s are required to be power sequence independent. In such SOC’s, IP level safe-stating is handled by safe-stating level shifters at various boundaries where IP designers use various type of cells to detect supplies and safe-state level shifter’s input and output. Many power domain signal crossing errors are found in the last stages of SOC design or in silicon, which results in heavy cost penalties either in terms of time to market or silicon respin.  A standard method is needed to indentify power domain crossings and deploy voltage detectors to generate safe-stating signals for level shifters at these crossings to keep inputs and outputs at known safe states.  In this paper we explain, in nut shell, important aspects of a framework that allows achieving this objective.

 

Problem Definition

Many power domain signal crossing errors are found in the last stage of SOC design or in silicon, which results in heavy cost penalties either in terms of time to market or silicon respin. A standard method is needed to indentify power domain crossings and deploy voltage detectors to generate safe stating signals for level shifters at these crossings to keep inputs and outputs in known safe states.

 

Proposed Solution

In this paper we proposed a standard scalable framework for:

§   Power domain signal crossing’s and interfaces definition,

§  Safe stating signal generation at specifically defined voltage levels

§  A standard overall architecture that can reduce errors and improve reusability with less verification and validation overhead.

The explained method can be formulated at an abstract level for application in a SOC with arbitrary number...