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Browse Prior Art Database

Self-Aligned FinFET Gate Contact on Device Area

IP.com Disclosure Number: IPCOM000241938D
Publication Date: 2015-Jun-09
Document File: 9 page(s) / 169K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method of making a self-aligned FinFET gate contact on the device area. This conceptual representation demonstrates the ability to save on the traditional area required to form gate contacts by forming the gate directly on the Fin transistor channel area.

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This is the abbreviated version, containing approximately 52% of the total text.

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Self-

-Aligned FinFET Gate Contact on Device Area

Aligned FinFET Gate Contact on Device Area

FinFETs offer area and performance advantages over traditional planar FETs due to the vertical nature of a large subset of the total transistor width. Unfortunately, discrete transistor-to-transistor spacing and contact landing areas to each of the transistor nodes negate a large subset of the area advantages FinFETs enable. Gate contacts are particularly area expensive as, traditionally, that connection must be made well away from the transistor channel area to mitigate the work function modulation frequently associated with making connections within the transistor body area as well as minimizing the possibility of gate contacts shorting to either diffusion. This notion allows a connection within the gate body area of a metal gated FinFET, utilizing a novel self-aligned technique.

    Adding gate connection landing pads outside the transistor area is the historic approach to avoiding any interaction between the contact definition, etch, and subsequent fill, and the charges in the gate dielectric or modifying the physical work function of the device itself. This approach is most applicable on FinFETs, and when metal gates either replace metal gates or gate first metal gates are used.

    This notion allows a connection to be made within the gate area itself, eliminating the large additional area to make an off device gate connection as well as the large input capacitance increase associated with off transistor gate connections. Moving the gate contact to the area above the body of the transistor saves significant area as well as mitigates the gate capacitor load. The process steps follow:
normal fin island definition, tailoring implantations, etc.


1.

gate dielectric deposition


2.

gate level deposition


3.

etch stop film deposition over the gate level conductor. Assume silicon nitride in this


4.

example. It might be desirable to have a thin SiO2 between the Gate and the SI3N3. If so, an extra etch will...