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DT-to-DT Fin Short Mitigation using Pre-Epitaxy HCl Etch of Poly-Si:As

IP.com Disclosure Number: IPCOM000241988D
Publication Date: 2015-Jun-11
Document File: 4 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a new flow applied to enhanced Dynamic Random Access Memory (eDRAM) integration that forms a strap connection and minimizes the risk of shorting by controlling the epitaxy (EPI) growth on the poly fin (strap) region.

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DT-to-DT Fin Short Mitigation using Pre-Epitaxy HCl Etch of Poly-Si:As

In state of the art enhanced Dynamic Random Access Memory (eDRAM) integration, epitaxy is required in the DT-to-fin strap region in order to lower the strap resistance. With the POR flow, part of the fin (in DT region) is poly, so the epitaxy (EPI) grows much faster and shorts to an adjacent node. To prevent this, it is important to control the EPI growth on the poly fin (strap) region.

The novel solution is a new flow to form a strap connection and minimize the risk of shorting.

Post recess 2, poly 3 is Silicon (Si)-poly (doped with Arsenic (As)). This is known art. After PC and spacer formation, before performing a negative Field Effect Transistor (nFET) epitaxy, the process etches off (time controlled) the upper part of the Si:As poly and the Si:As-poly strap portion of the fin using Hydrochloric Acid (HCl) in the EPI chamber. (Gaseous Hydrogen Chloride (HCL) etches arsenic doped Silicon very fast, arsenic doped poly-Si is even faster, without measurable etching silicon; only a short etch time needed, such as 5-15 seconds, depending on etch temperature.) During actual nFET EPI, the EPI grows from the sidewall of the fin and from the exposed poly regions of the DT, which still merge and form the strap, but minimize the overgrowth from DT region, thereby minimizing DT-to-DT shorts.

The following figures represent the components and process for implementing the novel solution.

Step 1

Step 2

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