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Low Leakage III-V FinFETs

IP.com Disclosure Number: IPCOM000242055D
Publication Date: 2015-Jun-16
Document File: 5 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use wide bandgap materials to serve as spacers and reduce leakage currents.

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This is the abbreviated version, containing approximately 73% of the total text.

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Low Leakage III -

III-V transistors are susceptible to high leakage currents, due to the narrow bandgap and mechanisms such as band-to-band tunneling and direct source-to-drain tunneling. Fin Field Effect Transistor (FinFET) architectures are important to continue scaling to 14nm and beyond; therefore, use of III-V in semiconductor technologies mandates a III-V FinFET device.

The novel solution is a method to use wide bandgap materials to serve as spacers and reduce leakage currents.

The method forms III-V FinFETs using a gate-last process. After dummy gate formation, the method cuts the and recesses the ends of the fins . Wide bandgap material (e.g., Indium Phosphorous (InP)), epitaxy (epi) grows from the ends of the fins. This material is then etched using the spacer as a hardmask , forming a thin, wide bandgap spacer between the channel and the source /drain regions. Spacer formation, epitaxy, and etch can be performed multiple times with different epi doping levels , or ion implantation, to optimize dopant profiles. The method performs source/drain (S/D) epitaxy, and standard replacement metal gate (RMG) FinFET processing continues.

Figure 1: Grow relaxed graded layer III-V semiconductor on substrate ending in device III-V material (i.e. InGaAs (known Art))

Figure 2: Pattern III-V fins

-V FinFETs

V FinFETs

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Figure 3: Pattern dummy gate

Figure 4: Form spacer

Figure 5: Etch ends of fins using spacer as a self-aligned mask

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Figure 6:...