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Source Voltage control to satiate hold margin in MUX based scan design during scan shift Timing

IP.com Disclosure Number: IPCOM000242066D
Publication Date: 2015-Jun-17
Document File: 3 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Abstract: Disclosed is a method to reduce the number of hold violations in a chip by having reduced voltage specification during the scan shift mode over functional mode of operation of an SOC. There by number of additional buffer padding on the Q to SI path can be reduced in huge numbers and hence the area can be saved which is of no use post manufacturing test.

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Source Voltage control to satiate hold margin in MUX based scan design during scan shift Timing

Background:

In a typical SOC, DFT Scan Test by Automatic Test Pattern Generation is commonly used technique to detect manufacturing defects. Max based Scan architecture is the widely used technique in the industry. These scan -D flip flops introduce Hold violations by architectural construction due to clock skew in implementation. Also, these hold violations need additional care in Test timing closure. Since the scan shift path is a one to one connection, they are more susceptible to hold violation. Widely used techniques include, adding lock-up latch / hold delay buffer / repeater padding to fix these violations on the scan shift path.

    Since these paths of scan shift are sparingly used in design during functionality, they are of no use in functional mode of the chip after manufacturing test. These additional buffers added to fix the hold violations also increase the chip area, active power and leakage power when operating in functional mode.

Description:

The proposed method in this art minimizes the effort of fixing the hold violations in a mux scan flop based scan architecture in scan shift mode. The proposed technique achieves this by

performing the scan shifting at a different voltage level.

Figure 1 above illustrates the different sets of voltages that can be used to close timing during the functional and test modes. This disclosure takes advantage of the phenomenon where in a typical SOC scan architecture would have a different voltage specification for scan shift mode. The voltage specification of functional mode and all other modes of the SOC, including the scan

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capture mode would remain same.

The...