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Optimized common library cell for functional clock gating and scan shift (lock-up).

IP.com Disclosure Number: IPCOM000242079D
Publication Date: 2015-Jun-18
Document File: 3 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Manufacturing Test - (Design for Test in general terms) is mandatory for any SOC ( system on chip). It needs additional logic to be added to the functional/Real logic to support the manufacturing test. This additional test logic helps in generating Automatic Test pattern generation to test the manufacturing defects. So that one can evaluate the quality of the product before shipping it to customer. As mentioned above the additional test logic is one time useful while testing the design and will be never used in actual usage of the product. Optimization of test logic is always been a challenge to reduce the overhead of chip area and timing, multiple patents and papers are presented to address this area. This paper is also targeted to reduce the redundant test logic by leveraging the existing latch inside an integrated clock gating circuit of functional logic and reuse it as a lock-up latch in the scan shift mode In the normal functional /scan capture mode the proposed cell acts as a functional clock gating cell and in the scan shift mode this can be used as lock-up latch with the clock as pass through.

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Optimized common library cell for functional clock gating and scan shift (lock-up).

Optimization of test logic is always been a challenge to reduce the overhead of chip area and timing, multiple patents and papers are presented to address this area.

This paper is also targeted to reduce the redundant test logic by leveraging the existing latch inside an integrated clock gating circuit of functional logic and reuse it as a lock-up latch in the scan shift mode.

The proposed idea is to leverage the existing latch inside a ICG (Integrate clock Gating circuit) cell and reuse it as a lock-up latch in the scan shift mode with additional MUX.

In the normal functional /scan capture mode this proposed cell acts as a functional clock gating cell and in scan shift mode this acts as lock-up latch along with that it will allow the clock as pass through.

The clock gating cell functionality is to allow the clock during scan shift mode and during capture/functional mode of operation it will either block or allow the clock depend on the enable pin
settings. If the functional enable pin active it will allow the clock otherwise it will block the clock.

The typical usage of clock gating cell is to reduce the power by gating clock of the logic which not in use at that moment. Below circuit diagram showcases the typical clock gating cell.

Lock up latch is an other library cell which is commonly used in between flops of a same scan chain which are driven by two different clock sources, this is to adjust the skew on the data path to meet the hold...