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Browse Prior Art Database

Segmented Stacked FinFET for Improved Contact Resistance

IP.com Disclosure Number: IPCOM000242086D
Publication Date: 2015-Jun-18
Document File: 1 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to reduce the external resistance in stacked nanowire transistors. The solution is to use a segmented stacked silicon fin and source/drain (S/D) segmented stacked fins with segmented epitaxy, and then have a wrap-around contact around each fin.

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Segmented Stacked FinFET for Improved Contact Resistance

A method is needed to reduce the external resistance in stacked nanowire transistors. High external resistance is partially caused by the lack of contact area for silicidation and metallization. In order to mitigate this effect, a wrap-around contact is proposed herein. However, in order to maintain tight fin pitch, a simple wrap-around contact cannot be used, because not enough space is available for a wrap-around contact at tight fin pitches (e.g., 28nm). The lack of space is because, for a fin Field Effect Transistor (finFET) device that is 70nm tall, for example, the source-drain epitaxy extends past the fins and thus merges the one fin with the adjacent fin (28nm away). If the fins are merged by the source/drain (S/D) epitaxy, then a contact cannot wrap around each fin individually, because there is no space in between the fins for the contact to wrap around.

The novel solution is a method to use a segmented stacked silicon fin and S/D segmented stacked fins with segmented epitaxy, and then have a wrap-around contact around each fin.

To implement the method, first, a segmented fin stack is deposited on a silicon or Silicon on Insulator (SOI) substrate. This is done by depositing alternate layers of silicon and a dielectric material. Then, a conventional fin patterning and gate stack process and spacer process are performed, as is well known in the prior art. Then, source/drain epitaxy is performed. He...