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Close Proximity Sharp Junction for Future CMOS

IP.com Disclosure Number: IPCOM000242087D
Publication Date: 2015-Jun-18
Document File: 3 page(s) / 107K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve extension dopants (i.e. reduce extension resistance) and provide a sharp dopant profile for SCE control.

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Close Proximity Sharp Junction for Future CMOS

Current state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) technologies rely on the activation and in-diffusion of source/drain dopants into the perimeter areas of the channel by high-temperature processing steps, most commonly after embedded epitaxy and various ion-implantation steps. Typically, a trade-off is reached between sufficient dopant activation and minimized diffusion from the highly doped source/drain (S/D) regions to form the active junctions. This trade-off often ends with a highly resistant junction and degrades transistor performance

The novel solution is a method to form a source/drain extension closer to the channel than conventional methods provide. The final structure is different from what has been disclosed in the prior art.

A transistor is formed on a silicon or silicon on insulator (SOI) substrate, using methods well known in the prior art, up to and including gate formation, but not including spacer deposition. Then, a first dielectric spacer material is deposited conformally. The dielectric deposited is thin, to enable a thin first spacer. Then, the spacer material is etched, forming a sidewall spacer on the gate. Next, the S/D regions are implanted using germanium, with the implantation type being a pre-amorphization implant. The purpose of this implant is to pre-amorphize the source/drain up to a thickness of 5nm or so. Pre-amorphizing a region allows it to be selectively etched later in subsequent processing steps.

In the next step, a second spacer dielectric material is conformally depos...