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An Integrated Approach to Achieve Faster Lock-Time in Analog PLL

IP.com Disclosure Number: IPCOM000242127D
Publication Date: 2015-Jun-19
Document File: 6 page(s) / 256K

Publishing Venue

The IP.com Prior Art Database

Abstract

PLL’s usually have a lock time in the range of tens of microseconds. Any switch from one power mode to another must have an internal RC oscillator or external crystal as its clock source for the duration of the PLL lock. This leads to larger boot time for the entire power gated section of a SoC entering functional mode. If the PLL has a faster relock on such power mode transitions, all power gated modules of the SoC can be brought out of reset more quickly. The solution proposed in this paper is an integrated circuit that helps restore the configurations of the PLL on a relock event. This allows the PLL to be used as system clock when transitioning between different power gated modes, reducing the time to exit reset for all power gated components of the SoC.

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An Integrated Approach to Achieve Faster Lock-Time in Analog PLL

PLL’s usually have a lock time in the range of tens of microseconds. Any switch from one power mode to another must have an internal RC oscillator or external crystal as its clock source for the duration of the PLL lock. This leads to larger boot time for the entire power gated section of a SoC entering functional mode. If the PLL has a faster relock on such power mode transitions, all power gated modules of the SoC can be brought out of reset more quickly. The solution proposed in this paper is an integrated circuit that helps restore the configurations of the PLL on a relock event. This allows the PLL to be used as system clock when transitioning between different power gated modes, reducing the time to exit reset for all power gated components of the SoC.

In most current power efficient System-on-Chip (SoC) solutions, the integrated system frequently enters low power modes to conserve energy and springs back to action upon occurrence of suitable external/internal events. While entering these low power modes, the analog PLL is powered down and reactivated when entering normal mode of operation. As all the modules of such a system derive their clocks from the analog PLL, its lock time in such scenarios plays a crucial role in power down mode exit time.

It has been observed that most of the time, the PLL operating point remains the same before and after exiting such low power system modes. While there are many analog PLLs that have fast lock times, they take the same amount of time on each power down occurrence and subsequent reactivation, thus making the low power mode exit time of the system comparable to the time it takes for transitioning to normal operating mode after a power-on reset event.

The solution proposed here addresses such scenarios by drastically reducing the lock time of the analog PLL, through a combination of analog and digital approaches, when a system tries to reactivate it to an unchanged operating pointwhile transitioning to the normal mode from a PLL power down mode.

The motivation behind this integrated approach for analog PLL lock time reduction when trying to restore it to an unchanged operating point is:

•      To improve the overall system response time while exiting from a mode where analog PLL is powered down and reactivated with an unchanged configuration.

•      To eschew the need of analog PLLs with very fast lock time to address the scenario where the PLL operating point doesn’t change between PLL power down events.

•      To implement a consistent solution to address such scenarios independent of the type of System-on-Chip environments.

The following are the schemes used in this integrated approach.

Implemented on Analog PLL

•         A scheme to calibrate the analog PLL for a particular operating point and regaining it in much less time with the help of pre-calculated calibration values and configuration settings, upon reactivation.

Implemented as Digi...