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USING DOCSIS PROTOCOL MONITOR FOR FPGA SINGLE-EVENT-UPSET MITIGATION IN CABLE MODEM TERMINATION SYSTEMS

IP.com Disclosure Number: IPCOM000242178D
Publication Date: 2015-Jun-23

Publishing Venue

The IP.com Prior Art Database

Related People

Yang Kong: AUTHOR [+6]

Abstract

Presented herein is a method and system for mitigating Single-Event-Upset (SEU) Failures In Time (FIT) in Field Programmable Gate Array (FPGA) devices. Most Cable Modem Termination Systems (CMTS) deploy large FPGAs in data and control paths. Accordingly, mitigation of errors due to SEUs is important for enhancing system reliability and improving customer satisfaction.

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USING DOCSIS PROTOCOL MONITOR FOR FPGA SINGLE-EVENT-UPSET MITIGATION IN CABLE MODEM TERMINATION SYSTEMS

AUTHORS:

 Yang Kong Yie-Fong Dan Zhizhou Li David Peng

Huaidong Lou Shi-Jie Wen

CISCO SYSTEMS, INC.

ABSTRACT

    Presented herein is a method and system for mitigating Single-Event-Upset (SEU) Failures In Time (FIT) in Field Programmable Gate Array (FPGA) devices. Most Cable Modem Termination Systems (CMTS) deploy large FPGAs in data and control paths. Accordingly, mitigation of errors due to SEUs is important for enhancing system reliability and improving customer satisfaction.

DETAILED DESCRIPTION

    A FPGA is a Static Random Access Memory (SRAM) based technology device. The rate of SEUs (e.g., a bit flip of a memory element) in FPGAs are much higher than in Application Specific Integrated Circuit (ASIC) devices, since SRAM is more likely to be affected by radiation.

    Memory in FPGA devices include Configuration Random Access Memory (CRAM) and data memory. SEUs in data memory (e.g., Block RAM, distributed RAM, or registers) can lead to corrupt data flow(s) but will not affect FPGA behavior. However, SEUs occurring in CRAM may lead to unpredictable FPGA behavior, especially if the SEU affects a sensitive bit in CRAM.

    In the event that the SEU affects a sensitive bit in CRAM, unexpected system interrupts or error interrupts may be triggered, and corresponding interrupt handling

Copyright 2015 Cisco Systems, Inc.
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mechanisms may be implemented. In some cases, SEUs can even lead to traffic drops or result in cable modems going off-line. Typically, CMTS do not receive hardware-based interrupt signals, e.g., caused by SEUs. Accordingly, SEUs are effectively silent and recovery of service is not performed until a customer of CMTS calls to complain of poor service.

    Although built-in hardware features exist to detect SEUs and correct CRAM errors in modern FPGA devices, e.g., SEU events may be reported to a control plane by different kinds of SEU interrupts that can identify single bit or multiple bit events of each FPGA, SEU detection and correction is not sufficient for CMTS system reliability. Most SEUs will not impact sensitive bits of CRAM, and therefore, reloading the system whenever a SEU is detected will lead to poor system performance. Moreover, not all SEUs are correctable, and in some cases, logic corruption may still be present even after correction of a SEU in CRAM, e.g., in the case of an error in a state machine or an error in a logic loop.

    This solution provides a SEU handling mechanism for CMTS by utilizing a Data Over Cable Service Interface Specification (DOCSIS) protocol traffic monitor to determine the health of a FPGA data path. CMTS Software (SW) can implement error handling mechanisms for SEUs, detected by hardware-based designs as well as by the DOCSIS protocol traffic monitor.

    This method greatly reduces CMTS silent failures caused by SEUs (which may accompany a traffic drop), and also, may be easily pr...