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State Based Leakage Reduction for Sequential Architectures

IP.com Disclosure Number: IPCOM000242303D
Publication Date: 2015-Jul-06
Document File: 6 page(s) / 661K

Publishing Venue

The IP.com Prior Art Database

Abstract

In a current trend of SoC design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Low power consumption is very important in standby/stop modes because of battery limitations. Dynamic power still can be controlled by various techniques. Clock gating the sequential logic is one such technique to save dynamic power consumption when a particular module/core is not required and only the state retention of the flops is required and the clock to the flops remains either at ‘0/1’ state to retain the last state. However such clock gated modules continue to leak power because power supply is still ON.

Our goal was to find the best suited inactive state of inputs of sequential logic that results in the least leakage consumption power in clock gating mode and sequential cell continues to retain the last state when the clock is gated off. There are multiple techniques to achieve the above goal. Some techniques require only minor changes in the clock gating entry/exit FSM while some techniques may require changes in flop architecture to achieve the reduced leakage power goal under clock gating conditions.

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State Based Leakage Reduction for Sequential Architectures

In a current trend of SoC design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.  Low power consumption is very important in standby/stop modes because of battery limitations. Dynamic power still can be controlled by various techniques. Clock gating the sequential logic is one such technique to save  dynamic power consumption when a particular module/core is not required and only the state retention of the flops is required and the clock to the flops remains either at ‘0/1’ state to retain the last state.  However such clock gated modules continue to leak power because power supply is still ON.

Our goal was to find the best suited inactive state of inputs of sequential logic that results in the least leakage consumption power in clock gating mode and sequential cell continues to retain the last state when the clock is gated off.  There are multiple techniques to achieve the above goal.  Some techniques require only minor changes in the clock gating entry/exit FSM while some techniques may require changes in flop architecture to achieve the reduced leakage power goal under clock gating conditions.

Technique #1 Changing inactive state of clock of SoC.

 

Inactive state of clock of SoC should be derived on the basis of:

   1) Difference in leakage power in ‘0’ and ‘1’ inactive stage of given sequential element architecture used in SoC.

    2) Difference in leakage power in ‘0’ and ‘1’ inactive stage of given technology node used in SoC.

It would be advantageous if inactive state selection is based on above criteria and not through conventional way of always putting the clock to ‘0’ state for gating for:

          1) Significant leakage power saving whenever sequential logic is clock gated.

          2) Minimal design change and easy to implement.

Let’s consider a case to understand how the leakage can be varied for the different architecture of FF with the clock gated to ‘0’ or ‘1’. Consider a portion ‘C’ of FF as in Fig. 1.  When CP is gated i.e. ‘0’ then ‘A’ & ‘B’ are ON while ‘C’ & ‘D’ are OFF. Capacitance gets charged at the nodes ‘x’ & ‘y’.

Fig. 1 Leakage analysis for structure ‘C’ (a portion of FF) when CP is ‘0’.

For m3, its source terminal is at > 0V & for m2, its source terminal is at < vdd providing back-bias to the m2 & m3. A, B & C are stacked structures which saves more power when gets OFF due to the BODY-BIAS effect as capacitance gets charged to some potential which makes any transistor’s source terminal at > gnd potential(for nmos) & < vdd potential (for pmos) while their substrate remains at perfect gnd & vdd &hence increases the Vt of the transistor. D structure does not show such behavior as it is not a stacked structure.

Fig. 2 depicts two different architectures of Flip-Flop fo...