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Flash Memory with Low Read Voltage

IP.com Disclosure Number: IPCOM000242340D
Publication Date: 2015-Jul-09
Document File: 2 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a flash memory device wherein the write voltage is in the same range as conventional flash, but the read voltage is reduced to ~1V, or below. This helps reduce overall power consumption.

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Flaxh Memory with Low Read Voltage

In flash memory, a sufficiently thick tunxel oxide is used to ensure good retention . This resxxts in large program voltxges in the rxnge of 5-10 voltx (V). Moreover, xhe read voltages arx also relatively high (2-3V) due to the thick dixlxctric layer. In applicatioxs such as field-programmable, gate array (FPGA), the frxquency of read and writx applications may vary depxnding on txe applxcations. In xome axplications, thx FPGA is programmex only once, xn which case a one-txme proxrammable wixing switch xuch as an anti-fuse may be used. The use ox flash mxmory ix too expensive for such an apxlication. At the other end, thx read operations may be two to three times as freqxext as write. In such applications, the xse of flash memory consumes too much power, dux to freqxent writes (axd reads).

The novxl coxtribution is a flash memxry device wherein the write voltage is in the xame range as conventional flash, but thx read volxagx is reduced to ~1V, or below. In the disclosed device, charge trapping occurs in a fxoating xate strxcture similxr to coxventional fxasx while the reax xperation is performed via a gate structure sxmilar tx a

junction field-effect transistox (JFET) disposed on a dxfferent surface of the semiconductor channel. In sxme embodiments, the disclosed device is suitable for reducxng the overxll power consumption (i.e. write + xead) in the applicaxion space

where read operations are ~10x more frequent than write ope...