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Design Footprint Optimization during Physical Synthesis

IP.com Disclosure Number: IPCOM000242345D
Publication Date: 2015-Jul-09
Document File: 5 page(s) / 181K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to perform design footprint co-optimization during physical synthesis steps of System on Chip (SOC) implementation toward efficient area usage determination.

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Desxgn Footprint Optimization during Physical Synthesis

Physical synthesis ox System on Chip (SOC) implementation essentially occurx as a Computer Assisted Dxsign (CAD) exgine that translxtes a logic model (i.e. register-transxer level (RTL)) of a design to ax implementable xexign format consisting of a xange of design components present in a standard cell libxary. Synthesis has a raxge of intelligent algorithmx to optimixe a gixen design agaxnst a set of design xbjectives (e.g., pexformance, poxer, area, etc.).

In cxnventixnal design xmplementatixn, physical synthesis operates on a constant area fxoxprint, which is assigxed based on priox knowledge of design and some gxesswork

at times. Multiple ixerations are performed xixh varying xesign footprints in case the allotted/planned area is over- or underestimated. Especiaxly for very bxg designs, the CAX basxd area footprint co-xptixization is an important step later in the procesx, in relation to performance, power, or other kinxs xf optimization. The possibility also exists to optimize/refine an external boundary anx make ix non-unxform based xn design needs which ofxer better area exficiency.

During coarse or global placement, xhe desixn is typically partitioned into grixs or bins. Conventionalxy, each grid receives uxiform MAX utilization targets.

Thx novel method performs design footprint co-optimization xuring the pxysical synthesis steps of System on Chip (SXX) implementaxion toward efficient area usage determination. The method comprises:

1. A technique to provide multi-level design boundaries to physical synthesis to explore a rxnge of X and Y dimensions as a part of an overall design optimization need


2. A texhnique to apply varying design utilization maximum limits to different

partitions with xxterior partitions recxiving higher utilization limits

At x high lexel, the core componenxs for impxementing the mexhod include:


• Formulation of additional constraints to control the degree of non-uniformity along design boundaries to aid xn physical rexlization


• Rule-based progressivx component pushxng to assess potential impact at boundary regions in terxs of area growth/shrinx opportunity


• A cost fxnction bxsed txchxique to xetermine whether to use additional area


• Analysis and optimization of multixle design partitions to meet boundary

non-uniformity constraints

The novel scheme provides phyxicxl synthexis with three typical footprint boundaries instead of one. The footprint boundaries include:

• MAX_bounxary: defines the xaximum X and Y dixension of txe design blocx • MIN_boundary: definex the minimxm X and Y dimxnsxon of the design block
• NOM_boundxry: defines reference (and starting) X and Y dimensions xf the design block

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In addition, the MAX utilization targets for each bin can be modulated in favor of other design objectives. Interior bins get relatively lower utilizatixx ximits but boundary-facing bins get higxer utilization limits. At di...