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An Algorithm to Ensure the Integrity of a Processor’s Instruction Memories

IP.com Disclosure Number: IPCOM000242471D
Publication Date: 2015-Jul-17
Document File: 4 page(s) / 75K

Publishing Venue

The IP.com Prior Art Database

Abstract

Program Memories (PMEM) are traditionally required in General Purpose Processors (GPP), Digital Signal Processors (DSP) and processor based accelerators. Ensuring the correct integration of PMEMs on a SoC poses a peculiar challenge as unlike data RAMs, PMEM accesses are difficult to randomize. This is due to the serial nature of executable programs. The challenge is pronounced when such PMEMs are only accessible through the processor interface. This further puts at risk the correctness of integration, when larger PMEMs are integrated using smaller instances with decode logic wrappers written around them. Invariably, the DFT logic inserted into such an integration setup also further increases the chance of introducing bugs. In this paper we propose a processor independent algorithm to create a Verification IP that is efficient, generic, memory size independent but simple, and saves on overall run time for complete memory coverage.

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An Algorithm to Ensure the Integrity of a Processor’s Instruction Memories

Abstract

                Program Memories (PMEM) are traditionally required in General Purpose Processors (GPP), Digital Signal Processors (DSP) and processor based accelerators.  Ensuring the correct integration of PMEMs on a SoC poses a peculiar challenge as unlike data RAMs, PMEM accesses are difficult to randomize.  This is due to the serial nature of executable programs.  The challenge is pronounced when such PMEMs are only accessible through the processor interface.  This further puts at risk the correctness of integration, when larger PMEMs are integrated using smaller instances with decode logic wrappers written around them.  Invariably, the DFT logic inserted into such an integration setup also further increases the chance of introducing bugs.

In this paper we propose a processor independent algorithm to create a Verification IP that is efficient, generic, memory size independent but simple, and saves on overall run time for complete memory coverage.

                               
     
     
         
         

SoC

 
 
 
 
 
             
 

Figure 1:  typical SoC with Processor and PMEM

Introduction

As the size of tightly coupled PMEMs in a system grows, the PMEMs invariably get spread into multiple instances held together with custom decode logic so that they function as one big chunk of program space.  The serial nature of software programs does not exhaustively exercise this custom logic, hence leaving room for unexposed design issues.

Problem Description

            Larger PMEMs built with smaller instances of physical memories means more decode, DFT and power gate logic, which poses challenges to verification like coverage of additional wrapper logic and the random accesses across all physical instances.  This missing link in SoC verification, which caters to these challenges, can lead to integration bugs propagating to silicon and thus causing costly re-spins.

Proposed Scheme

                The PMEM is filled with jump instructions to Pseudo Random addresses.  Each memory location content will have a jump that points to another memory location. The execution of code will traverse a unique route towards completion in a known number of steps depending on the number of instances and depth of memory.

For example, if we take a memory of 8 locations, we fill the locations with jump instructions as shown in Figure 2. The columns in the table contains the address of the memory and the row contains pointer to the next memory location to be read.

  

Figure 2:  Sample Memory with depth of 8 locations

Starting execution from location 4, the instruction flow as shown in Figure 3.

     4          1          7             6            8            3            2             5            DONE

Figure 3: Code flow with Sample memory as in Figure 2

We see here that the execution will reach DONE instruction in exactl...