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Automatic Assertion Generator For Connectivity Check

IP.com Disclosure Number: IPCOM000242473D
Publication Date: 2015-Jul-17
Document File: 4 page(s) / 181K

Publishing Venue

The IP.com Prior Art Database

Abstract

SOCs (silicon on chip) are becoming more and more complex. Connectivity verification has become a big challenge, such as pad multiplexor design, glue logic and gasket connection. This connectivity verification work costs much time and effort using dynamic simulation. In this paper we present a method to generate assertions automatically and then check the connectivity by formal method. The proposed method strengthens the current IFV (Incisive Formal Verifier) flow, which cannot generate assertions automatically.

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Automatic Assertion Generator For Connectivity Check

ABSTRACT

SOCs (silicon on chip) are becoming more and more complex. Connectivity verification has become a big challenge, such as pad multiplexor design, glue logic and gasket connection.  This connectivity verification work costs much time and effort using dynamic simulation.  In this paper we present a method to generate assertions automatically and then check the connectivity by formal method.  The proposed method strengthens the current IFV (Incisive Formal Verifier) flow, which cannot generate assertions automatically.

KEYWORDS

Assertion, connectivity, automatic, generator, check, formal

1.      INTRODUCTION

SOCs have become more and more complex. Connectivity verification is a big challenge, such as pad multiplexor design, glue logic and gasket connection.  In the current flow, we need to run dynamic simulation to check the connectivity.  In the current IFV flow, we also need to write assertions according to the pad multiplexor design then run the IFV.  These two methods take a lot of time and effort.  We propose a method to generate the assertion automatically according to the design code, and then do the connectivity check with these assertions.

2.      WHAT IS THE MOTIVATION?

We have encountered some problems with current SOC connectivity check flow.

(a)    Current EDA tools cannot generate the assertion automatically for IFV. Verification engineer need to write the assertion by hands according to the pad multiplexor design. It will cost much time and effort. Sometimes the assertions are not equivalent to the real design.

(b)   There is no good formal method to check the correctness of SOC/subsystem connectivity in the early stage of the project. With dynamic simulation, it will cost much time to debug and the bugs couldn’t be found in the early stage.

3.      The flow of automatic assertion generator for connectivity check

In order to resolve the above problems, we have developed a method to generate the assertion automatically according to the design code and then check the connectivity with these assertions.

Fig 1. Usage flow

Ÿ  Design code: this design code could be described as C, SystemC and HDL language, no...