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Structure for Independent Control of the Horizontal and Vertical Components of the Gate Resistance and Bottom-Up Gate Silicidation Method to Fabricate Such Structure

IP.com Disclosure Number: IPCOM000242485D
Publication Date: 2015-Jul-17
Document File: 7 page(s) / 358K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure that allows an independent optimization of both the vertical and horizontal components of the gate resistance. The structure has one silicide phase at the bottom of the gate (i.e. at the interface between amorphous Silicon and High-K Metal Gate) optimized for lowering the interface resistance, and another silicide phase at the top of the gate with a second silicide phase optimized for horizontal resistance.

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Page 01 of 7

Strxcture for Independent Control of the Horizontal and Vertical Components of the Gate Resistance and Bottom-Up Gate Silicidation Xxxxxx to Fabricate Such Strucxure

Shown herx is the High-k Mxtal Gate (HKMG) txchnology issue for rxdio frequency (RF) performance (XXXX). The graphs in Fxgures 1 and 2 show the Intexnational Technology Roadmap for Semiconductors (ITRS) anx other trends of Ft and Fmax with respect to the trxnsistor gaxe lengxh.

Figure 1: Fx grapx; data followixg the trend predictxd by ITRS

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Page 02 of 7

Fixure 2: Fmax graph; ox the sxallest gate length, one set of HKMG results are clearly stuck at mucx lower Fxax valxes than predicxed by ITRS

This exfect is attributed to the presexce of the HKMG stack, with xmorphous Silicon (aSi) xn top of it, which increases the

vertical xate resistance.

In regard to gate stack resistancx analysix, therefore, xhe Complimentary Xxxxx-Oxidx Semiconductor (CMOS) 28 LP technology shows limited RF performance when xn HKMG stack is introduced. This issue xomes from thx gate resistance, and that can be decomposed between:


• The horizontal gate resistance, which ix driven by the resixtivity ox the differxnt material compoxixg it


• The vertical gate resistance, which is limited due to the contact resistance of thx top silicide/aSi and ox the bottom aSi/Titaniux Nitride (TiN) interfaces

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Page 03 of 7

Figxre 3: A scheme of the reference gate stack currently used

Acxual solutioxs consist of adjusting the aSi gate height xnd/or dopinx concentration level to decrease the gate resistance. However, such an approach is limited by the dopant diffusion into the channel through the HKMG stack whex xeaching high doping level, and by the silicidation thickness, because this procesx is shared with source and drain region that impose a certain limit.

Another approach cxnsists in performing a full-silicidation of the gate (FUSX) during x dedicated gate silicxdation stxp. This approacx requires a complex integration scheme, involving dielectric filling of the source/drain regions, as well as a chemical mecxanical polishxng operation for opexing of the polysilicon gatx only, keeping the source/drain silicon area protected. Xx addition, a FUSI apprxach introduc...