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Multi-Data Flip-Flop and Flip-Flop Merge Method

IP.com Disclosure Number: IPCOM000242558D
Publication Date: 2015-Jul-24
Document File: 4 page(s) / 276K

Publishing Venue

The IP.com Prior Art Database

Abstract

Flip-flop, also known as register, is an important part of IC (Integrated Circuit) design. Flip-flop is used to hold data, so chip state can be controlled. Usually one flip-flop has one corresponding function-data-input. This paper proposes a multi-data flip-flop with a multi function-data-input and an extra select pin to choose which function to use. Also one flip-flop merge method is proposed to combine different flip-flops into one multi-data flip-flop. Memory BIST (Build In Self Test) logic is used as an example to apply multi-data flip-flop and flip-flop merge methodology. With this method, chip area and power is saved.

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Multi-Data Flip-Flop and Flip-Flop Merge Method

Abstract

Flip-flop, also known as register, is an important part of IC (Integrated Circuit) design. Flip-flop is used to hold data, so chip state can be controlled. Usually one flip-flop has one corresponding function-data-input. This paper proposes a multi-data flip-flop with a multi function-data-input and an extra select pin to choose which function to use. Also one flip-flop merge method is proposed to combine different flip-flops into one multi-data flip-flop. Memory BIST (Build In Self Test) logic is used as an example to apply multi-data flip-flop and flip-flop merge methodology. With this method, chip area and power is saved.

Introduction

Flip-flop is an important part of IC design. In today’s SoC (System on Chip) design, flip-flop takes about 40-50% ratio of total SoG (Sea of Gates) area. Flip-flop is used for data retention, so system state can be controlled. Figure 1 shows one regular master-slave scan flip-flop schematic, which combines 42 transistors. Under clock control, function data “d” enters into master latch through input stage, and then output and preserved in slave latch. Compared to combination logic, flip-flop only provides data-retention "function”. So this makes it possible to share different flop-flops into one as they all have same function.

Figure 1. Regular master-slave scan flip-flop schematic

 
 

Design and Implementation

To merge different flip-flops into one, multi-data flip-flop is proposed. As shown in Fig. 2, multi-data flip-flop adds 6 transistors at input stage of regular flip-flop. There are two data inputs “D1” and “D2”, chosen by new select pin “sel”. When “sel”=0, function data “D1” is selected; and when “sel”=1, function data “D2” is selected.

Figure 2. Multi-data flip-flop input stage schematic

 
 

With the multi-data flip-flop, it is possible to merge different flip-flops into one multi...