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Diagonal Power Grid for Improvement in IR Drop

IP.com Disclosure Number: IPCOM000242619D
Publication Date: 2015-Jul-30
Document File: 4 page(s) / 151K

Publishing Venue

The IP.com Prior Art Database

Abstract

Power grid design is becoming difficult to meet the increasing power requirements of the System on Chip (SoC) with various analog and mixed signal IP’s being integrated in the same SoC. Analog IP’s have dedicated and isolated power supplies on die that have stringent parasitic requirements. Due to this, global power grid gets discontinuous and meeting IR drop becomes challenging. We propose a power grid design in which the grid extends diagonally with respect to the chip and also vertically and horizontally (at 45 degrees). This type of grid can be used in top or thick metal layers (like AP layer) where signal routing is not done. By using this grid, utilization of the design can be increased and also congestion can be lessened by using fewer lower or thin metal resources for the power grid. This type of grid also helps in achieving IR drop with even wire-bond packages.

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Diagonal Power Grid for Improvement in IR Drop

Power grid design is becoming difficult to meet the increasing power requirements of the System on Chip (SoC) with various analog and mixed signal IP’s being integrated in the same SoC. Analog IP’s have dedicated and isolated power supplies on die that have stringent parasitic requirements. Due to this, global power grid gets discontinuous and meeting IR drop becomes challenging. We propose a power grid design in which the grid extends diagonally with respect to the chip and also vertically and horizontally (at 45 degrees). This type of grid can be used in top or thick metal layers (like AP layer) where signal routing is not done. By using this grid, utilization of the design can be increased and also congestion can be lessened by using fewer lower or thin metal resources for the power grid. This type of grid also helps in achieving IR drop with even wire-bond packages.

                                                                Figure 1: Conventional Power grid in AP layer

Generally AP (Aluminum cap) layer is used only for the power grid of the SoC in either horizontal or vertical directions. Consider the AP layer direction is horizontal as shown in purple in Fig 1, then power and ground sources are spread all over the chip.  As can be seen in Fig. 1, sources (represented by white dots) present at the corners (NE, SE, SW and SE) do not contribute enough current.  Also, the sources that are present in the orthogonal direction (N, S) of the AP layer are not contributing enough current because they carry current in lower metal layers whose resistivity is higher than that of the AP layer.

               

Figure 2: Conventional grid with a proposed grid style

Our aim is to get current to the center of the SoC through all ineffective sources (N, W, NW, NE, SE, SW) using the least resistance paths, as shown in Fig 2.  So for pads located at the corners, a diagonal grid provides the shortest path (by Pythagoras’s theorem).  In Fig 2, the white arrows represent the diagonal grid.  The shortest resistive path for sources present at the N an...