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Method to Reduce Leakage Power

IP.com Disclosure Number: IPCOM000242621D
Publication Date: 2015-Jul-30
Document File: 3 page(s) / 477K

Publishing Venue

The IP.com Prior Art Database

Abstract

IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Low power consumption is very important in standby/stop modes because of battery limitations. Dynamic power can be controlled by various techniques like frequency scaling/supply voltage lowering and clock gating. Clock gating the sequential logic is one such technique to conserve dynamic power consumption when particular module/core is not required and only the state retention of the flops are required. But still the logic consumes the same amount of leakage whether the clock has been gated or not, so it is very important to reduce leakage power with some mechanism in the critical power saving mode where clock is gated. During the high phase of the clock for a positive level triggered flip-flop, if the value of TE can be changed, leakage may be reduced because the positive edge triggered flip-flop would not capture the valid data at the high phase of the clock. Generally, leakage power can be saved by lowering the supply voltage (VDD) but this comes with additional overheads like expensive and bulky supply switches that can affect die-size requirements and performance may be degraded.

Any flip-flop architecture has scan enable (TE) signal associated with it, which is a signal that has already been routed to all the flip-flops. Generally during the high phase of the clock in normal mode or during the gating of clock, scan enable signal remains at 1’b0 as the mode as a type of functional mode itself.

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Method to Reduce Leakage Power

IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Low power consumption is very important in standby/stop modes because of battery limitations. Dynamic power can be controlled by various techniques like frequency scaling/supply voltage lowering and clock gating. Clock gating the sequential logic is one such technique to conserve dynamic power consumption when particular module/core is not required and only the state retention of the flops are required. But still the logic consumes the same amount of leakage whether the clock has been gated or not, so it is very important to reduce leakage power with some mechanism in the critical power saving mode where clock is gated. During the high phase of the clock for a positive level triggered flip-flop, if the value of TE can be changed, leakage may be reduced because the positive edge triggered flip-flop would not capture the valid data at the high phase of the clock. Generally, leakage power can be saved by lowering the supply voltage (VDD) but this comes with additional overheads like expensive and bulky supply switches that can affect die-size requirements and performance may be degraded.

Any flip-flop architecture has scan enable (TE) signal associated with it, which is a signal that has already been routed to all the flip-flops. Generally during the high phase of the clock in normal mode or during the gating of clock, scan enable signal remains at 1’b0 as the mode as...