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Test Method Using Dedicated Code Loading Module

IP.com Disclosure Number: IPCOM000242622D
Publication Date: 2015-Jul-30
Document File: 5 page(s) / 568K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method to download the test code into the system memory via a dedicated “Test Loader” module is presented. The test loader bypasses the interconnect fabric used in a multi-master systems for accessing the internal memories and instead provides a dedicated interface between the chip periphery and internal system memories to download the test code. It enables downloading the test code every clock cycle, thereby using the full bandwidth of the chip interface. The test loader provides the flexibility to download the code at any memory location and of any size. The number of peripheral pins required is configurable based on requirement of a SOC.

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Test Method Using Dedicated Code Loading Module

Abstract

A method to download the test code into the system memory via a dedicated “Test Loader” module is presented. The test loader bypasses the interconnect fabric used in a multi-master systems for accessing the internal memories and instead provides a dedicated interface between the chip periphery and internal system memories to download the test code.  It enables downloading the test code every clock cycle, thereby using the full bandwidth of the chip interface. The test loader provides the flexibility to download the code at any memory location and of any size. The number of peripheral pins required is configurable based on requirement of a SOC.

Introduction

For testing the maximum operational frequency (Fmax) of a single or multiple cores in a SOC, a test code is loaded into system’s internal memory via Automated Test Equipment (ATE) and the core is made to execute the test code. Conventional methods generally use interfaces like general purpose I/Os or external memoryinterface to download the test code from chip interface to internal memory. These interfaces utilize the existing interconnect fabric to access the internal memories. There are generally multiple stages of gasket/protocol convertors in the data path as shown in Figure 1. Due to these gasket/protocol convertors, a single write transaction to the internal memory can take multiple clock cycles leading to increased test time.

Proposed Method

In the proposed method, the existing interconnect is bypassed for downloading the test code into the system memory and instead a dedicated module “Test Loader” is implemented which provides a dedicated interface between the chip periphery and internal system memories to download the test code as shown in Figure 1. TL_CNTL and TL_DBUS[n-1:0] pins are required from chip peripheral to interface to Test Loader module. TL_CNTL is single bit and TL_DBUS can be of any width (minimum single bit) depending on SOC requirements.

Proposed method provides the following features

•         The code can be downloaded into the system memory every clock cycle.

•          The code can be downloaded at any memory location and of any size.

•         The code can be downloaded into non-contiguous memory locations thereby providing full flexibility in downloading the code as per the linker scripts.

Figure 1 : System level connectivity for Test loader

Test loader block diagram and operation

Figure 2 shows the block diagram for Test loader. Test loader is enabled only during the test mode and will be disabled during the functional mode. This is controlled by gating the TL_CTL pin with test mode signal. Test loader consists of the following blocks

Configuration capture: This block captures configuration data like Memory no. , Memory data size count and code download start address. Memory no. indicates to which memory block code is to be downloaded. Start address indicates at which memory address to start downloading the...