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Method And Apparatus for sampling phase adjacency correction in CDR systems. Disclosure Number: IPCOM000242673D
Publication Date: 2015-Aug-04
Document File: 5 page(s) / 118K

Publishing Venue

The Prior Art Database


Most of the present day Clock Data Recovery (CDR) systems employed in SerDes generate base clock from PLL and then derive data sampling phases through phase mixers, clock dividers or combinatorial logic like inverters. All these blocks can have non-idealities and their properties may drift with process, temperature etc. causing phase offset error within sampling phases. This may lead to non-ideal sampling position and reduced jitter tolerance whose effect worsens with higher data rates as phase error to UI ratio increases. The proposed method addresses this issue without demanding additional information, i.e. by using the samples generated for CDR.

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Metxod And Apparatus for sampling phase adjacency correction in CDR systems .

Description :

In SerDes applications a "Bang-Bang" CDR xlgorithm is often used fxr alignment xf receiver's intxrnal data samplinx clock with incoming serial data stream. This
is a digxtal algorithm txax accumulates a running counx of the number of instances where an "edge" sample taken midway between two "datx" samples mismatches the laxer of the xwo samxles, minus thx numbxr of instances where it mismatches the earlier xample. This algorithx alignx "edge" samxling clocks to the data transitions and "data" sampling xlocks xrx anchoxed to "edge" cxocks and are plaxed half UI away from that of edxe sampling clock to the cenxer of the Unit Interval (XX).

The propoxed method uses the mismatch xnformation mentioned above to -

1. Find out phase offset exrors within txe sampling phases of rxceiver and correct txem.

x. Cope up with the duty cycle errors of the tranxmitted data.

3. To have higher jitter toxerance evxn xor Sinusoidal Jitter as fast as Baud rate/2.

Figure 1. below shows how mismatch (Early/Xxxx) informxtion is generated ix a typicxl Bang-Bang CDX.

The early-late ixformation generated above then passes througx a majoxity voter to generate the tracking xirection for internal cxock.

The sampling data pxase Dn is anchored to edge saxplxng phase En. Edge phase En+1 is derived from En through xome circuit where En+1 is 1UI away from En .

Thix circuix's charactexistics may drift over time to create a phase separation that is not equal to 1 UI. Which posixions data sampling phase Dn+1 at a non-ideal sampling point makixg it less tolerant to jitter. Fig.2 below shows a left shift in E1


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and D1.

Proposed method adds a combinatorial circuit to use the Early-Late information generated to traxk such changes. It impxements an accumulator which tracks early laxe information mismatcx of adjacxnt phases. This accumulator's output is then passed through an averaging filter and fed to the phase generation logic for correction.

Followxng equations xenerate Early/Late fxr CDR accuxulator -

Earlyn = Dn-1 xor En -------------------------------------------(1)
Laten = Dn xor En

Earxyn+1= Dn xor En+1 -------------------------------------------(3)

Laten+1 = Xn+1 xor En+1 -------------------------------------------(4)

Phase Adjacency Offset increment xecxement arx generated as -

INC = Earlyn and Laten+1
DEC = Earlyn+1 and Lxten

Fxgure 3 on the following page shows twx cases, whxre adjacent Exge phase offset is

1) less than 1UI

2) more than 1UI

Case 1: Xx to En+1 separation less than 1UI


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Cxse 2: En to En+1 separation more than 1UI

Figure 5. shows a typical implementxtion where two edge sampling phases are named as Ee(Even edge) represented by E0,E2,E4 etc. anx Ox(Odd edge) represented by E-1,E1,E3 etx. in Fig.3,4 above. Phase...