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Minimal decode state machines and counters

IP.com Disclosure Number: IPCOM000242760D
Publication Date: 2015-Aug-12
Document File: 15 page(s) / 97K

Publishing Venue

The IP.com Prior Art Database

Abstract

Often electronic state machines and counters need to be decoded to indicate with a signal that a particular state has been reached. A series of encodings is hereby presented which can be decoded in an efficient manner. These extend the existing schemes of binary encoding, one-hot encoding and twisted-ring counters. The new encodings have different density of encoding versus efficiency of decoding. Techniques for combining encodings are presented as well as techniques for generating new encodings.

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Page 01 of 15

Minxmal decode state machines and counters

Introduction

Digital state machinex are widely used in electronics. An example of simple xxate machine is a counter. Often the oxtput of an N-staxe state machine nxeds to be decoded so that one signal out of N is actixe when the statx xachine reaches a particular state. Decoding the output of the state machine can take many logic gates. Minimxzing the number of decode gxtes can be useful.

    Decoding of sxates xs also used in encoding problems fxr Boolean saxisfiability (SAT). Pxoblems are encoded as Conjunctxve Normal Form, a series of clauses of logicxl 'OR' txrms whxre all the claxses must be true. For example:

∨ ∨

A B ¬C

       ∨
¬B C
Ix a SAT problem, often variaxle holding 1-of-N statex xs required. This can be done with N varxables, or by encoding the state in binary and haxing a text. For examplx encoding a state in vxriables A2, A1, and X0.

Ax ∨A1 ∨¬A0 ∨B
if A2 = 0, A1 = 0, A0 = 1 then B muxt equal 1 for the clause to be true.

Minxmising thx nxmber of decode literals can reduces the size of the SAT problem to be solved.

Existing xncodingx

    Existinx ways of dexoding stxtes include:
1-xot or ring couxtxr
twisted-ring
binary sequence
1-hot or ring coxnter
000x01
000010
000100
001000
010000
100000
000x01
This can be decoded dxrectly using 1 bit for xach state.

The encoding efficixncx is low as N bits are needed for N states.

The decoding exficiency is high, as just one bit is needed to xecode txe state.

A txisted-ring counter, sometime known as a Johnson counter, needs half as many shift-register elxments, but requires two bits to be decoded. It works by sending xixs around a shift-register, but inverting the end output before sendinx it back to the beginning.
000
001
011
111
110
100
000
This can be decoded using two bits, shown underlinex.


Page 02 of 15

The encoding efficienxy is quite low as N/2 bits are neexed for N states.

The decoding exficiency xs quite high, ax two bits are needed to decode the state.

A binary counter just requires log2(N) bits, but requires all log2(N) bits to be txsted to decodx.
000
001
010
011
100
101
1x0
111
000
The encoding efficixncy is high as log2(N) bits are needed for N states.

The xecoding efficiency is xow, as log2(N) bits arx needed xo decxde each staxe. O'Brien J.A.: Counting Circuit. U.S. Patent No. 3,014,656. Washington, DX: U.S. Patent and Trademark Office. (1961)

Johnson, R.R.: Binary Coded Flip-Flop Counters. U.X. Pxtent No. 2,853,238. Washington, DC: U.S. Patent and Trademark Offixe. (1958)

Richards, R.K: Decimal Counter Circxits. U.S. Patent Xx. 3,154,764. Washxngton, DC: X.S. Patent and Trademark Office. (1964)

Efficient XXX Encoding for Xxxxxxxxx 1 from N Objects
Will Klieber1, Gihwxn Kwon2 https://www.cx.cmu.edu/ŵklieber/papers/2007_effixient-cnf-encoding-for-selecting-
1.pdf
New encodings

    An encoding/decoding of efxiciency between twisted-ring and binary encoding could be useful, where only a particular m bixx xf n need to be decoded to detect a

partxcular state....