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Detecting Tester Indeterminism Caused by Synchronizers

IP.com Disclosure Number: IPCOM000242810D
Publication Date: 2015-Aug-19
Document File: 5 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

The addition of two stage or three stage synchronizers at asynchronous interfaces adds to indeterminism in SoC design, which can lead to issues if the design has not taken care of all the scenarios. Such issues are generally caught in the Gate Level Simulations (GLS) or on silicon. To mitigate the risk and the cost factor, there should be a way to catch such issues early in the design cycle. The solution to this problem can be found by modeling the effect of meta-stability through a testbench module file that forces “X” on the output of the first sync flop and then enabling the propagation of meta-stability through the simulation tool. The tool will then evaluate the conditions for both ‘0’ and ‘1’ in a single run and ideally it should converge at one value if the design has no issues. If the values diverge, ‘X’ is propagated in the design, which indicates that the behavior is indeterministic. The RTL has to be analyzed and fixed for these diverging points.

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Document Title

Detecting Tester Indeterminism Caused by Synchronizers

Abbreviations

1.      SoC : System on Chip

2.      CDC : Clock Domain Crossing

3.      TX – RX :  Transmit – Receive

4.      RTL :  Register Transfer Level

Abstract

The addition of two stage or three stage synchronizers at asynchronous interfaces adds to indeterminism in SoC design, which can lead to issues if the design has not taken care of all the scenarios. Such issues are generally caught in the Gate Level Simulations (GLS) or on silicon. To mitigate the risk and the cost factor, there should be a way to catch such issues early in the design cycle. The solution to this problem can be found by modeling the effect of meta-stability through a testbench module file that forces “X” on the output of the first sync flop and then enabling the propagation of meta-stability through the simulation tool. The tool will then evaluate the conditions for both ‘0’ and ‘1’ in a single run and ideally it should converge at one value if the design has no issues. If the values diverge, ‘X’ is propagated in the design, which indicates that the behavior is indeterministic. The RTL has to be analyzed and fixed for these diverging points.

BODY

Multiple clock domains on SoCs often require the addition of multi-stage synchronizers between asynchronous interfaces. Such an addition of sync stages eliminates issues related to CDC but at times can give heartburn to the SoC:

1.   Indeterminism at the interface owing to meta-stability at the output of the first flop can cause cycle-jumping issues, seen during pattern runs on the tester where the same test when run over multiple times, yields “cycle-shifted” or “cycle-jumped” output at IO interface.

2.    Indeterminism in data paths may lead to functional failures in certain...