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Duty Cycle Aware Clock Tree Synthesis

IP.com Disclosure Number: IPCOM000242833D
Publication Date: 2015-Aug-21
Document File: 5 page(s) / 2M

Publishing Venue

The IP.com Prior Art Database

Abstract

Modern day EDA solutions build clock trees for insertion delay, clock skew and clock power, but at lower technology nodes NBTI, PBTI and other aging effects are more prominent, which degrade clock duty cycle leading to silicon failures, so it becomes important to maintain clock duty cycle. This paper presents a clock tree synthesis methodology that maintains clock duty cycle right by construction.

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Duty Cycle Aware Clock Tree Synthesis

Abstract

Modern day EDA solutions build clock trees for insertion delay, clock skew and clock power, but at lower technology nodes NBTI, PBTI and other aging effects are more prominent, which degrade clock duty cycle leading to silicon failures, so it becomes important to maintain clock duty cycle. This paper presents a clock tree synthesis methodology that maintains clock duty cycle right by construction.

Problem Definition

Usually quality of CTS is measured on following parameters Insertion Delay, Skew and Power. As we are going down the technology nodes NBTI, PBTI and other aging effects degrade clock duty cycle leading to silicon failures; so another CTS parameter comes into the picture i.e., Duty cycle degradation. Larger SoC sizes and performance intensive designs running at higher frequencies further aggravate this problem. Currently there is no solution for maintaining the clock duty cycle as current methods only work on maintaining trigger edge skew.  Further, there currently is no exhaustive and reliable STA check to catch the duty problem upfront.

- Pulse width check (passing check does not guarantee reliability after aging).

           - STA with aged libraries (not present for all technology nodes)

            - Aging spice simulations (not exhaustive and impossible to run on across PVT and on full design)

Proposed Solution

The objective of our approach is to modify the design in such a manner that any EDA tool by virtue of design constructs a balanced clock tree, where both rise and fall clock delays are matched, thus improving the duty cycle.

The algorithm for our proposed solution has the following parts:

            Dual Edge Flop Crea...