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Adaptive Self-Heating Circuit Control

IP.com Disclosure Number: IPCOM000242943D
Publication Date: 2015-Sep-01
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design solution that uses small temperature sensing circuits that are placed strategically in a distributed device or circuit array to sense local temperature deltas and/or absolute local temperature. The output signal of the sensors is processed by a control unit that generates a negative feedback control that adjusts the buffer drive strength to the limit of predetermined thermal setting.

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Adaptive Self -

Semiconductor devices consume power and heat up. If the heat cannot be conducted away quickly enough, then the semiconductor device temperature can be many degrees hotter than the semiconductor chip background or average temperature. This local temperature increase of a single device above the chip background temperature is referred to as device "self-heating." Two identical adjacent devices with a large difference in power consumed will be at very different self-heating temperature rises above the chip background temperature. The device with the larger power consumption will heat the most. The self-heating generally depends on power consumed per device area, so making the device larger with the same total power consumption reduces the self-heating temperature rise.

     This self-heating temperature rise of a device, above the chip background or average temperature, also raises the temperature of operation of device connected contacts and metal interconnects of the device. One of the most significant failure mechanisms of semiconductor chip metal interconnect system is electromigration where current flow in the interconnect actually moves metal in the interconnect and causes connection shorts or opens over time. This metal movement is exponentially dependent on the interconnect temperature. So, a 10 degree C rise in interconnect temperature could cause a doubling of the electromigration failure rate. Stated another way, to mitigate the effect of a 10 degree C self-heating temperature rise in the interconnects, the current carrying capacity of the interconnect would have to double. This usually means a metal line; for example, would have to double in size or width. This larger size also increases parasitic capacitance that increases device power dissipation and hurts its performance. It is not unusual, in modern 3-D finfet processes, to have unmitigated self-heating temperature rises of 60 degrees C at high device power densities which would result in 16 times metal size or 2x for each 10C temperature rise.

    The optimum solution usually involves techniques to cool the device by lowering its power density. Stated another way, the device needs to dissipate lower power per unit area so it must get bigger. Unfortunately, bigger also usually means more parasitic capacitance with its associated lower performance. Solutions to date have required that the device be made large enough or its power density reduced enough to lower the self-heating temperature rise for the pathologically worst case scenario. For semiconductor processes, this is usually highest chip background temperature, worst case chip operating mode, and worst case device conditions for maximum power dissipation (i.e., max power supply voltage and semiconductor process point for maximum power dissipation). So every operating usage mode, temperature, and process build point is penalized the maximum amount in performance.

    Another problem that this invention address...