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Controlling EMI by Means of Varying the Duty Cycle of the Clock in Digital Electronics

IP.com Disclosure Number: IPCOM000242944D
Publication Date: 2015-Sep-01
Document File: 4 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method of controlling the EMF emissions from the IT hardware. While the most common method is using the Spread Spectrum clocking, another mechanism for achieving comparable results is proposed here - adjusting the Clock Duty Cycle.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 42% of the total text.

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Controlling EMI by Means of Varying the Duty Cycle of the Clock in Digital Electronics

EMI/EMC often presents a tough challenge in commercial electronics arena. Spread Spectrum clocking is one of the most popular ways of reducing the emission in general. But there is always a need to improve the EMI further and do so in a most economical way possible. Because the emissions can be affected by a variety of design factors and attributes of the system, electrical and mechanical, the final round of EMC tests can only be done when the system is in its final and shippable electrical and mechanical form. And, that means that such EMC test is done a short time before the GA date. Therefore, if any EMC issues are discovered, there is always a possibility of a need for a high-risk design change, and some design changes are not even feasible being as close as it usually is to the GA date. Based on that, it's highly desirable to have as many nondisruptive "levers" as possible to control the EMI. Proposed here is one such "lever".

    Varying the Duty Cycle of the clock allows to change the even/odd harmonic composition of the clock waveform, and thus the composition of the emission. At exactly 50% duty cycle, the clock waveform is represented by its fundamental and odd harmonics. As the duty cycle start moving away from the 50% point, the even harmonics appear in addition to the odd harmonics still being present. More on the specifics of it is in the next section.

    PLLs of the clock chips and PLLs of most ASICs do not offer the user any control over the duty cycle of the clocks that they generate. The spec of the Duty Cycle is usually stated very broadly as a 40% - 60% range. The spectral difference between the clock within this range is huge. Not being able to control the duty cycle tightly within this range is a lost opportunity. Here

are the two main implications of not being able to control the clock duty cycle better:
- not being able to reduce/eliminate some of the harmonics if they become the EMC offenders, and having to rely on other means like gaskets and filter which are the Hardware EC's
- the test systems that do pass the EMC compliance test may in fact not be representative of the total population of systems; i.e., the test systems will have certain duty cycle of the clock

(collection of all clocks) within the 40% - 60% range, and the systems with other values of the duty cycles will not have been tested. And while the range of the duty cycles for the manufactured product can be anywhere in the 40% - 60% spread, it means that some of the production systems can be greater EMC offenders than the EMC-tested system and possibly violate the FCC limits.

    Introduce the direct explicit control over the Duty Cycle at the clock PLL level. The control is programmable. The Duty Cycle is also affected by the asymmetry of the transition times. This can be addressed too. However, it's a different aspect of the Duty Cycle. This disclosure mainly meant t...