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Circuit structure for modulo arithmetic of narrow data in wide data flows

IP.com Disclosure Number: IPCOM000242945D
Publication Date: 2015-Sep-01
Document File: 3 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an adder/subtracter with built-in zero and sign extension

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 76% of the total text.

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Circuit structure for modulo arithmetic of narrow data in wide data flows

Many 64-bit architectures use a programming language model for C, C++, Java*, and other languages with 32-bit integers. When these integers are used in conjunction with 64-bit values, and in pointer arithmetic when used in a 64-bit address space, the 32-bit value needs to be explicitly extended to 64-bit values with "extend sign" and "zero extend" instructions. Some architectures specify 32-bit operations that automatically zero- or sign-extend results to 64-bit to simplify modulo arithmetic as used in the C, C++, Java and other languages. However, sign extension comes at a significant cost to fan out a sign bit to/from bit 31 to bits 32 to 63, plus associated muxing.

    In accordance with the present invention, extension of a 32-bit intermediate result to a 64-bit zero- or sign-extended value is accomplished by preconditioning the input operands in the 64-bit data path to eliminate separately controlled high-order word overrides and the associated fan-out (see Figure 1 below).

Figure 1

    
To perform zero extend in conjunction with narrow width modulo operations, precondition high-order bots and a break in the carry chain is provided. In another embodiment, the bit capturing the carry-out from the low-order 32-bit result can be overridden by way of a single bit multiplexer (see Figure 2 below).

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Figure 2

    
To perform sign extend in conjunction with narrow width modulo operations, swi...