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Synchronized I2C FSM Implementation for Master and Slave Operation

IP.com Disclosure Number: IPCOM000243119D
Publication Date: 2015-Sep-16
Document File: 2 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

I2C is most widely used serial interface to communicate with the external devices. One approach to design the I2C protocol is to use unsynchronized I2C bus signals to the host clock in the design implementation. Use of Unsynchronized I2C clock (SCL) and I2C data line (SDA) in design will pose lot of challenges. In this paper we propose an approach that synchronizes SCL and SDA with high frequency host clock, which addresses the challenges of earlier unsynchronized bus signal designs.

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Synchronized I2C FSM Implementation for Master and Slave Operation

                             


Abstract

I2C is most widely used serial interface to communicate with the external devices.

One approach to design the I2C protocol is to use unsynchronized I2C bus signals to the host clock in the design implementation. Use of Unsynchronized I2C clock (SCL) and I2C data line (SDA) in design will pose lot of challenges.

In this paper we propose an approach that synchronizes SCL and SDA with high frequency host clock, which addresses the challenges of earlier unsynchronized bus signal designs.

Keywords

I2C state machine, I2C implementation, I2C FSM, I2C design/RTL.

Introduction

I2C is a 2-wire protocol widely used for two way data communication. In order to increase the re-usability of the module and to avoid the additional clock domain crossing logic, it’s useful to have synchronized I2C design to the host clock. Here is a list of challenges for asynchronous I2C protocol implementation:

·         Special STA checks are required to avoid erroneous start and stop condition detection.

·         If the I2C module is supposed to work in run mode (when host clock is ON), ensuring the data integrity would be a major challenge as there is a clock domain crossing (CDC) of data. If there is multi bit data to be transmitted from a continuously generated data, FIFO kind of structure needs to be used. Depending upon the data width hardware area will increase. 

·         Need for CDC verification of the design.

·         For different SoC’s with different data transfer requirements, module re-usability is reduced as clock domain crossing has to be re-designed as per SoC use case or requirement (For example, shared mailboxes, semaphores kind of structure and periodic data transfer from DSP and external I2C is continuously reading the data).

In order to have an I2C interface of smaller area and interface synchronously to SoC clock domain, which eliminates the clock domain crossing issues from SCL to host/module clock and vice versa, a design using a state machine is proposed that supports feature list of I2C protocol.

Proposed Design Approach

In the proposed design, I2C bus signals...