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High Precision sampling circuit design for improved system control

IP.com Disclosure Number: IPCOM000243283D
Publication Date: 2015-Sep-18
Document File: 6 page(s) / 323K

Publishing Venue

The IP.com Prior Art Database

Related People

Douglas Edward Smith, Bob Hart, John Rogers and Robert Aleksa: INVENTOR

Abstract

A variety of applications utilize analog to digital converters (ADC) to convert a continuous analog signal to a discrete digital signal. During the conversion of the analog signal to a digital signal there will be some uncertainty in the input voltage, called sampling error. An RC sampling circuit is employed to reduce the error in the ADC by supplying the current to the ADC necessary for the sampling process. A problem with the existing RC circuits is that they increase the settling time. Most ADCs have a limited amount of time (called tracking time) to get an accurate analog reading. Thus increased settling time leads to lesser performance. This paper illustrates a method that delivers the necessary current to the ADC with reduced sampling time, and improved accuracy to a degree not achievable with existing RC, ADC circuits

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Page 01 of 6

High Precision sampling circuit design for improved system control

Douglas Edward Smith, Bob Hart, John Rogers and Robert
Aleksa ABSTRACT

A variety of applications utilize analog to digital converters (ADC) to convert a continuous analog signal to a discrete digital signal. During the conversion of the analog signal to a digital signal there will be some uncertainty in the input voltage, called sampling error. An RC sampling circuit is employed to reduce the error in the ADC by supplying the current to the ADC necessary for the sampling process. A problem with the existing RC circuits is that they increase the settling time. Most ADCs have a limited amount of time (called tracking time) to get an accurate analog reading. Thus increased settling time leads to lesser performance. This paper illustrates a method that delivers the necessary current to the ADC with reduced sampling time, and improved accuracy to a degree not achievable with existing RC, ADC circuits.


1. Introduction

The basic principle of operation of a precision analog to digital converter (ADC) is to convert a physical quantity to a digital quantity. These converters are used for many applications such as in gyro circuits, momentum control circuits, general applications, space products etc. The accuracy of the analog to digital converter depends on the sampling error. The ADC sampling error is caused by the high frequency sampling process which leaves an uncertainty in the acquired voltage.

The sampling error in an ADC is reduced by adding a buffer stage amplifier followed by an RC network prior to the ADC input. A typical method for minimizing precision ADC sampling error as given in the prior art is shown in Figure 1.


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The capacitance in the RC network is connected to ground or to a complementary input. The purpose of the capacitor is to provide a decoupling charge to fill an internal ADC sampling capacitor quickly and accurately during the digitally multiplexed sampling process.

Very low impedance can be used in the RC circuit to reduce the sampling error. Space applications, though require a resistance larger than the recommended value in order to reduce currents during fault conditions. These large resistors increase settling time due to feeding of the capacitive load to ground, and increased DC offsets. The capacitors to ground also have high variation leading to lesser performance in getting the reading. The capacitor variation can range from 30% to 50% in a space environment. Capacitors to ground also increase the settling time of driving amplifiers thereby decreasing the ADC performance. Increased settling time also increases the channel to channel cross talk in internally or externally multiplexed ADC systems. This crosstalk also degrades the sampling performance.

Therefore a solution is needed that address the limitations of RC circuits mentioned in the prior art, as described above.

Figure 1 - Prior Art



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2. Solution

The proposed i...