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HIGH FREQUENCY GATE DRIVER CIRCUITS HAVING LOW ELECTROMAGNETIC INTERFERENCE EMI EMISSIONS

IP.com Disclosure Number: IPCOM000243619D
Publication Date: 2015-Oct-06
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

A gate drive circuit with ultra low electromagnetic interference EMI emissions is disclosed The gate drive circuit is used for high frequency and high temperature power conversion applications The gate drive circuit disclosed herein employs an ultra fast miller clamping to mitigate driving voltage Vgs spikes during turn off due to the induced current associated with high rise and fall of voltage from a secondary to a primary side dv dt effects Further to reduce the cross talking effect a triple winding structure for an isolation transformer is disclosed that significantly reduces primary to secondary winding capacitances

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HIGH FREQUENCY GATE DRIVER CIRCUITS HAVING LOW ELECTROMAGNETIC INTERFERENCE (EMI) EMISSIONS

BACKGROUND

 

The present disclosure relates generally to gate drive circuits and more particularly to a high frequency gate drive circuit having low electromagnetic interference (EMI) emissions.

Gate drive circuits are generally associated with large rates of rise and fall of voltage from a secondary to a primary side (dv/dt) during the switching transients and cross talking phenomenon for phase-leg switching. Conventional electromagnetic interference (EMI) emission mitigation techniques are implemented at level of a converter with extra EMI common-mode or differential-mode filters. Further, cross-talking phenomenon mitigation techniques are usually implemented by reducing primary-to-secondary windings of the transformer of the gate drive supply voltage. However, such conventional mitigation techniques have limited efficiency at the high frequency operations.

It would be desirable to have an improved gate drive circuit having low EMI emissions.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 depicts the triple winding structures for the ultra-low primary-to-secondary winding capacitances of a gate driver isolation transformer.

Figure 2 depicts reduced primary-to-secondary capacitances of the isolation transformer.

DETAILED DESCRIPTION

A gate drive circuit with ultra-low electromagnetic interference (EMI) emissions is disclosed. The gate drive circuit is used for high frequency and high temperature power conversion applications. The gate drive circuit disclosed herein employs an ultra-fast miller clamping to mitigate driving voltage (Vgs) spikes during turn-off due to the induced current associated with high rates of rise and fall of voltage from a secondary to a primary side (dv/dt) effects. Further, to reduce the cross-talking effect, an improved winding structure for an isolation transformer is disclosed that significantly reduces primary-to-secondary winding capacitances.

Figure 1

Figure 1 depicts the triple winding structures f...