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High Voltage Stress Testing HVST Technique using Flexible Voltage Regulator

IP.com Disclosure Number: IPCOM000243654D
Publication Date: 2015-Oct-07
Document File: 3 page(s) / 172K

Publishing Venue

The IP.com Prior Art Database

Abstract

We propose in this paper a new HVST method and implementation for simultaneously stressing all different supply domains and devices of an integrated circuit enabling to save test time and minimize overall product cost Apparatus used is implemented using an on chip programmable voltage generation allowing to avoid the need of dedicated connections PADs for different stress voltage levels A Method allowing the HVST testing in regulated mode is also proposed

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High Voltage Stress Testing (HVST) Technique using Flexible Voltage Regulator  

Abstract

We propose in this paper a new HVST method and implementation for simultaneously stressing all different supply domains and devices of an integrated circuit, enabling to save test time and minimize overall product cost. Apparatus used is implemented using an on-chip programmable voltage generation allowing to avoid the need of dedicated connections (PADs) for different stress voltage levels. A Method allowing the HVST testing in regulated mode is also proposed.

Introduction

Burn-in is one of the most widely-used accelerated testing methods in the industry to guarantee the reliability and quality. Unfortunately burn-in process is high cost, time and resource consuming. The reduction of the burn-in test time is among most important in today’s IC manufacturing. To stay competitive in the IC market, manufacturers need to consider if burn-in is really necessary and there are other alternatives to provide customer satisfaction while minimizing the cost.

One of the methods that can be used to reduce or even eliminate burn in is the High Voltage Stress Test (HVST). A good HVST test pattern should provide maximum transistor test coverage in the shortest time possible. Voltage regulators are widely used in large scaled integrated circuits. Line regulation prevents output voltage change when the supply is increasing (HVST configuration). Some sub IC parts using regulated supply voltage are not stressed in HVST testing.

Classical methods implemented in regulator (e.g. shunt mode) do not allow the HVST testing in normal operation mode, where the overall IC power consumption plays an important role. Widely employed techniques provide a bypass or shunt mode which disables the voltage generator. This solution does not allow an accurate control on the voltage regulator and has no drive capability which limit the normal operating condition.

In order to circumvent all the above mentioned limitations, and fulfill the HVST test requirements, we propose in this document a new method for simultaneously stressing all different supply domains and devices of an integrated circuit, enabling to save test time and minimize overall product cost. Besides economic aspects, it allows efficient electrical stress testing of the chip.

Design and Implementation

Optimal performance, low power consumption together with embedded BIST (Built-in-Self-Test) functions allows achieving high competitive products, while reducing test time and facilitating integration in a single package. Figure 1 shows a block diagram of the proposed apparatus. It is composed by the HVST control circuitry (100), a bandgap generator (200) and a voltage regulator (300). Bandgap generator (200) provides a process, voltage and temperature independent voltage reference (Vbg), which is the reference for the IC in the normal...