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Link recovery using lane merging in PCIe cable attached IO sub systems Disclosure Number: IPCOM000243768D
Publication Date: 2015-Oct-16
Document File: 8 page(s) / 170K

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The Prior Art Database


Disclosed is a method that enables faulted pcie lanes in a pcie link to merge together to form a functional pcie lane that in turn contributes to the pcie link formation. In this method, the failed pcie lanes which do not contribute to a pcie link, due to physical carrier problems, can be used to form a pcie link by lane merging method to improve the availabitlity of the pcie link.

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Link recovery using lane merging in PCIe cable attached IO sub systems

Disclosed is a method to improve the availability of the PCIe (Peripheral Component Interconnect Express) link between the PCIe endpoints. This method talks about the problem of pcie link width configuration and detection for pcie bridges/devices to PCIe Devices/IO Adapters especially using pcie cable attached IO. PCIe link is the point to point link between two pcie endpoints and the physical connection between these endpoints are called as pcie link. The pcie link is used to transfer the IO data in pcie packets over these links. The PCIe link contains the "PCIE Lanes" which are actual signal lines from the pcie device to pcie devices. There can be x1, x2, x4, x8 and x16 lanes configured between two pcie devices. These pcie "link training" will mark the speed and width at which the pcie link is operating on. This x1,, x4 are called as the pcie link widths and more width means, more data traffic that can be carried over the link between the devices.

The pcie cable attached io subsystems uses the fiber as the media of data transfer. Fiber is fragile and has more chances of being faulty or even break due to its physical structure. When using these pcie fiber cables in real systems for connection between two pcie devices,the pcie link will carry its pcie lanes over these fiber cables. If there is any fiber break or faulty, the corresponding pcie lane does not function and the pcie link training will either operate at degraded link width or even fail. For example, the normal x8 pcie link may operate at x4, 0r x2 or x1 or even no link at all based on which fiber goes down. If fiber that carries pcie lane 0 is broke, which will make it go down, or if it carries a lane 4 to 7 then the link width goes to x4 as per the pcie specification.

There are known solutions to this fiber faults/problems while carrying the pcie lanes. There are solutions which use extra fibers to accommodate these fiber failures and do the lane sparing with that extra/spared fiber in the connector. These lane sparing solutions are generally called 1:N sparing technique with single extra fiber. There is a immense need to actually to make use of the existing fibers itself on which the pcie lanes can be configured to route the pcie traffic. The cost of the cables and the time to do repair or replace with support maintenance becomes another factor, while the down time of the IO may be critical for the customers. This method will discuss the procedure to detect and configure the not working, faulty pcie lanes, (because of faulty fibers) and merge these fault lanes to make a logically functional pcie lane which can be used for carrying the pcie traffic on them. This method makes use of even the faulty fiber lanes to maximum extent to provide robustness to the pcie link by concept of "fault lane merging".

Each pcie lane consists of a full duplex communication with a transmit signals on TX wires and rece...