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Low Latency Hardware Random Number Generation by randomizing memory content

IP.com Disclosure Number: IPCOM000243797D
Publication Date: 2015-Oct-17
Document File: 3 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

This article describes a hardware random number generator (a hardware configuration and a method), that can generate at low latency, a stream of random numbers, that are near impossible to predict based on the operating conditions, and prior outputs.

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Low Latency Hardware Random Number Generation by randomizing memory content

This article describes a hardware random number generator (a hardware configuration and a method), that can generate at low latency, a stream of random numbers, that are near impossible to predict based on the operating conditions, and prior outputs.

Hardware random number generators (HRNGs) are designed to generate an unpredictable sequence of numbers. The major use for hardware random number generators, in today's semiconductor industry, has been in the field of data encryption, for example to create random cryptographic keys to encrypt data. These HRNGs are considered to be a more secure alternative to pseudorandom number generators (PRNGs), which may pass statistical pattern tests for randomness, but are vulnerable to attacks. In a PRNG, once the algorithm and the initial conditions (commonly referred to as "seed") is known, the output can be predicted, and does not remain secure any longer.

Hardware random number generators are usually based on microscopic phenomenon that are completely unpredictable in theory, such as thermal noise, process variations, photoelectric effect etc. Typically, they consist of a transducer that converts a physical phenomenon to an electrical signal, which is then amplified and digitized as required. One of the drawbacks of HRNG is that these phenomenon are relatively slow (i.e. high latency) which places a limitation on the ability to rapidly generate a random output sequence for encrypting large amount of data. An example of such an HRNG, would be a ring oscillator based RNG [1], where a slow clock, generated based on the amplification of thermal noise, erratically samples a fast clock to generate a random sequence. An enhanced, one-bit HRNG consists of back to back inverters, where in the feedback loop is enabled based on a clock [2]. The limitation of this approach is that the pattern is quite repeatable, unless additional steps are taken to ensure that the inverter are truly equal, which is a very difficult task to achieve across a large number of bits.

Main Idea

The basic idea of this article is to use a static random access memory (SRAM), and to create contention between different addresses of the memory to create randomization. Typically, during a write or read operation of an SRAM, only one of the 'N' addresses of an array bank are enabled. Enabling multiple address will lead to scrambling of the multiple digital data streams at each of those multiple address, creating a new data stream, based on the physical properties of the transistor, operating conditions (voltage and temperature) and the timing sequence of enablement. Each of these variables, adds an additional degree of randomness to the original scrambling process, thereby creation a third string that is nearly impossible to predict, even if the two original data strings are known. As such, we propose, a new mode of operation of an SRAM array, called 'rando...