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Hardware method to minimize rounding off error accumulation in running summation

IP.com Disclosure Number: IPCOM000243800D
Publication Date: 2015-Oct-17
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Hardware method to minimize accumulation of rounding-off error in running summation of any precision

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This is the abbreviated version, containing approximately 100% of the total text.

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Hardware method to minimize rounding off error accumulation in running summation

Disclosed is a system which minimizes accumulation of rounding off error while doing running summation.

Input is a data stream of any precision. It contains - a single-bit sign-bit (S), "Exp" bits exponent (Exp) and M-bits mantissa (Mantissa).

Max input data to min input data ratio is "2^R" i.e. R-bits for range value.

For each input, split it in two float numbers: "high-part float" and "low-part float".

Steps to create "high-part float" (Mask lower order R-bits of Mantissa - resulting number is high-part float):

1. High-part float mantissa = Input number bit-wise-and [1s (for (M-R) bits) from Most Significant Bit followed by 0s (for R-bits)]


2. High-part float exponent same as Input number exponent.


3. High-part float sign-bit same as Input number sign-bit.

Steps to create "low-part float":

1. Mask higher order (M-R) bits of Mantissa.

2. Calculate "leading zero detector" in lower order R-bits of mantissa. Say, lzd_of_R.

3. Adjust Exponent as: L_Exp = Exp - (M-R) - lzd_of_R 4. Adjust Mantissa as: L_Mantissa = lower R-bits of Mantissa << (M-R) + lzd_of_R
5. Sign-bit remains same as Input number sign-bit.

For every 2^R input numbers:


1. Sum-high = Accumulate high-part float numbers

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2. Sum-low = Accumulate low-part float numbers

Final-sum = Sum-high + Sum-low

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