Browse Prior Art Database

Rank Control Signal Multiplexing For Buffered Memory Systems Having Multiple Ranks

IP.com Disclosure Number: IPCOM000243856D
Publication Date: 2015-Oct-22
Document File: 5 page(s) / 184K

Publishing Venue

The IP.com Prior Art Database

Abstract

The method disclosed herein increases controls signals such as chip select (CS), clock enable (CKE) and ODT control (ODT) as the number of ranks increases to meet higher memory capacity demanded.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 76% of the total text.

Page 01 of 5

Rank Control Signal Multiplexing For Buffered Memory Systems Having Multiple Ranks

As higher memory capacity is demanded, the number of ranks needs to be increased . In this case, the number of rank control signals such as chip select (CS), clock enable (CKE) and ODT control (ODT) needs to be increased proportionally to the number of ranks. This is problematic due to pin count increase of memory controller and memory module.

This invention proposes to encode those signals when command and control signals are buffered between the memory controller and individual memory devices as in RDIMM, LR (Load-Reduced)-DIMM, or master-slave stacked memory device. Those encoded signals are decoded inside the buffer and original control signals are generated and fed to memory devices.

The figures 1 - 3 illustrate management of CS signals as the number of ranks are increased.

Figure 1 illustrates a plurality of buffered memory ranks.

Figure 1

Figure 2 illustrates a plurality of master-slaved memory ranks.

1


Page 02 of 5

Figure 2

Figure 3 illustrates a chip select information decoding table .

Figure 3

The figures 4 - 6 illustrate management of CKE signals as the number of ranks are increased.

Figure 4 illustrates a plurality of buffered memory ranks.

2


Page 03 of 5

Figure 4

Figure 5 illustrates a plurality of master-slaved memory ranks.

Figure 5

Figure 6 illustrates a CKE decoding table.

3


Page 04 of 5

Figure 6

Figure 7 illustrates a plurality of buffered memory ranks in accorda...