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Method for Handling Unplanned Integrated Circuit Reset or Corruption

IP.com Disclosure Number: IPCOM000243861D
Publication Date: 2015-Oct-22
Document File: 4 page(s) / 254K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for handling unplanned resets or corruption of integrated circuits that are used by computer systems to avoid undesirable behavior.

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This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 4

Method for Handling Unplanned Integrated Circuit Reset or Corruption

Disclosed is a method for handling unplanned resets or corruption of integrated circuits (ICs) that are used by computer systems to avoid undesirable behavior. Patents exist pertaining to IC resets and corruption. However, these deal more with designing the ICs to minimize unwanted internal resets and corruption, not handling when they inevitably happen. ICs cannot prevent external toggling of reset lines. This disclosure describes a method to handle unplanned resets and/or corruption.

    Integrated circuits (such as FPGAs, GPUs, or ASICs) in computer systems can be used to off-load specific functionality needed by the computer system. If the IC gets an unplanned reset or gets corrupted, in master/slave designs, the computer system must handle this and may need to reconfigure the IC for it to function properly. However, the computer system must be made aware of the reset/corruption before continuing to use the IC in the typical method. To prevent any undesirable behavior, this must be atomic - with every read of the IC there should be indication from the IC whether it was reset/corrupted before the computer system can treat the read as valid, and with every write of the IC, before the IC acts on the data, it should know whether to ignore the write if it has been reset/corrupted without the computer systems knowledge. This invention is a method for handling unplanned resets or corruption of ICs that are used by computer systems to avoid undesirable behavior.

    When the IC used by a computer system gets reset or corrupted in master/slave designs, it should inform the computer system (master) of this in case it needs to be reconfigured or otherwise re-integrated into the system. As the IC reset/corruption can happen at any time, this information must be returned and/or handled for every access (read or write). For example, the master cannot first read the reset/corrupted status from the IC and then write out data, as the reset or corruption could occur between the status read and the data write.

    In this invention, the IC will use a status/reset byte to communicate its current state. The status/reset byte can be defined in whatever manner is sufficient for the design. When the IC comes up after a reset or detects internal corruption, it will initialize or update the status/reset byte to a known clear state. As the computer system co...