Browse Prior Art Database

Self-Correcting Embedded, Fault Tolerant, Combined Random Access and Read Only Memory Method and Apparatus

IP.com Disclosure Number: IPCOM000243867D
Publication Date: 2015-Oct-22
Document File: 3 page(s) / 55K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a redundant ROM merged with a redundant register file or SRAM implementation which employs three ROM cells for each wordline/bitline crossing and majority function logic built into the read circuity to ensure that if one of the three cells is failing that the other two will still provide the correct data. This is useful but not limited to situations where a ROM and SRAM are combined within a memory.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 81% of the total text.

Page 01 of 3

Self-

Combined Random Access and Read

                            Combined Random Access and Read Only Memory Method and Apparatus

Unique memory structures are required to meet the complexity and performance requirements of processor architectures. Often these memory structures combine SRAM cells with ROM structures for a common decoded address. To improve yield on these memories, redundancy is sometimes required. If the memory has column redundancy, then a column must contain all SRAM cells or all ROM cells. If the memory has row redundancy, then a row must contain all SRAM cells or all ROM cells. This is a typical configuration. Redundancy for SRAM cells is one way to solve yield issues; however, when a ROM and SRAM are combined on the same bitline, redundancy becomes problematic due to the definition of how a ROM operates. ROM data is fixed and cannot be replaced by a spare row/column. A need exists for a method to combine SRAM and ROM redundancy in an array that will improve yield. In the following description, presented is an embedded self-correcting, fault tolerant, Read Only Memory (ROM) which solves the aforementioned problem.

    This publication describes a ROM implementation that employs three ROM cells for each wordline/bitline crossing. Figure 1 shows how the self-correcting fault tolerant ROM can be embedded in the memory structure and connected to the memory bitline without impacting the redundant controls of the memory itself. If a ROM cell were to fail causing one of the three...