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Method for Efficient Access in Hybrid Memory Systems

IP.com Disclosure Number: IPCOM000243872D
Publication Date: 2015-Oct-23
Document File: 4 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a hardware structure, for accessing data in hybrid memories, that eliminates the read-before-write problem (in the common case) while consuming less storage than the directory and not increasing the traffic from memory to the last-level cache (LLC).

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Method for Efficient Access in Hybrid Memory Systems

This disclosure addresses the problems of high power consumption and low capacity

while accessing data in hybrid memories. The novel contribution is a hardware structure that can eliminate this read-before-write problem (in the common case) while consuming an order of magnitude less storage than the directory , and not increasing the traffic from memory to the LLC.

One approach to reduce power consumption or increase capacity is to divide memory into a fast region and a slow region. To ensure fast access in a common case , memory data must move between the fast and slow regions based on the application's data requirements. This requires maintaining directory information for the data stored in the fast region. An area-efficient way of storing this tag information is to use spare bits (if any) available in the memory array itself. If the fast region is direct-mapped, then read accesses can obtain directory information with data. If the directory information matches, then the data can be used; otherwise, the slow region is accessed. (Figure 1) However, in case of writes, two accesses are required, first to read the directory information and, if it matches, the second to write the desired data to the memory location. This article uses the term "read-before-write" to describe this situation in hybrid memories. (Figure 2)

Figure 1: Introduction: Hybrid Memory (Fast and Slow DRAM)

Figure 2: Read-Before-Write Problem in Hybrid Memory

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Another solution is to store in the memory region identifier in the last -level cache(s) (LLC) of the system. For every block present in the LLC, a bit is stored in the corresponding directory to indicate whether the block is resident in the fast region . When the block is chosen for eviction from the LLC , if the block needs to be written back to the memory, this bit identifier for this block can be read to determine whether the fast/slow region of memory should be accessed. This solution does not have the "read-before-write" problem mentioned in the previous solution. However, in order to guarantee correctness, when the data moves from the fast to the slow region in the memory, this information has to be broadcast to all the LLCs of the system , and the corresponding entries in the cache directory have to be updated .

Another problem in organizing the fast region in hybrid memory is making it associative instead of direct mapped. However, this requires that accesses seq...