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Reset Domain Crossing Aware Synchronous Latch

IP.com Disclosure Number: IPCOM000243888D
Publication Date: 2015-Oct-26
Document File: 3 page(s) / 196K

Publishing Venue

The IP.com Prior Art Database

Abstract

Designs having multiple resets are prone to meta stability due to Reset Domain Crossing RDC events The issue becomes severe in cases where critical trim values such as PMC LVD HVD trims R C trims of RC oscillator etc need to be loaded and locked to avoid reloading and data corruption In such cases RDC events may result in incorrect values getting latched causing chip failure such as stuck in reset In this paper we propose a circuit and method for a synchronous latch that ensures output data is free from RDC issues

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Document Title:

Reset Domain Crossing Aware Synchronous Latch

Abstract:

Designs having multiple resets are prone to meta-stability due to Reset Domain Crossing (RDC) events. The issue becomes severe in cases where critical trim values such as PMC LVD/HVD trims, R/C trims of RC oscillator, etc., need to be loaded and locked to avoid reloading and data corruption.  In such cases, RDC events may result in incorrect values getting latched, causing chip failure such as stuck in reset.  In this paper we propose a circuit and method for a synchronous latch that ensures output data is free from RDC issues.

Problem Definition:

In a sequential design, if the reset of a source register is different from the reset of a destination register even though the data path is in the same clock domain, this will become asynchronous crossing path, which can cause meta-stability at the destination register during asynchronous reset assertion of the source register.  This is termed as a Reset Domain Crossing (RDC).  If this RDC issue is seen during latching of the values in a flop, it may result in latching of corrupted values.  This issue is most dangerous in designs where Power Management Controller (PMC) trim latching occurs since an incorrect or intermediate value may cause LVD/HVD events to occur, which may lead to the chip getting stuck in reset if the latch does not get cleared on LVD/HVD events.

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