Un-Aligned Store Handling in a Multi-Slice Microprocessor
Publication Date: 2015-Oct-29
The IP.com Prior Art Database
Described is a new mechanism whereby the un-aligned partial store data can be stored into multiple Data Caches (DCaches). Un-aligned store addresses will be sent to multiple slices, and then un-aligned store data will need to be written into DCaches of the respective slices.
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In a multi-slice design, the Data Cache (DCache) is partitioned into eight 8K blocks, with each block being Double Word (DW) aligned. There is one 8K DCache block per execution slice. Each DCache block can store one DW data per line. When a DW Store is unaligned, it will have to be stored into two adjacent DCache blocks. In order to store a DW, the store addresses and the store data will need to be sent to two DCache blocks. When a Quad Word (QW) Store is unaligned, it will have to be stored into three adjacent DCache blocks. In order to store a QW, the store addresses and the store data will need to be sent to three DCache blocks.
When a Store instruction is dispatched to the Issue Queue (ISQ), the ISQ will issue the store address to a slice's Load/Store Unit (LSU) when all of its source operands are available. The ISQ will then issue the store data to a LSU when the store's source operand is ready. Only one store address will be issued to the LSU. The respective receiving LSU slice will perform address generation on the issued instruction.
If the store address is DW unaligned, then the store address will be forwarded to two adjacent LSU slices. Each respective LSU slice will store the associated address into the Store Reorder Queue (SRQ). Then, single 64-bit store data will be issued from the ISQ to the LSU. Since the store DW is unaligned, the store data will be forwarded to two adjacent LSU slices. Each LSU slice will store its respective partial store data into the correct Store Data Queue (SDQ) and send its finish report to the Compl...