Browse Prior Art Database

Age Tracking of Instructions in a Non-Shifting Issue Queue

IP.com Disclosure Number: IPCOM000243948D
Publication Date: 2015-Oct-29
Document File: 3 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method of age tracking of instructions in a non-shifting issue queue.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 3

Age Tracking of Instructions in a Non -

Current implementations of an issue queue within a microprocessor typically involve a shifting issue queue. As an entry in the queue is selected for issue, the entries "above" are shifted down, and a newly dispatched instruction is always written into the "top" entry of the queue. As a result, all entries are actively clocked on every cycle, resulting in a significant increase in power consumption. The proposed non-shifting queue plus age array described in this disclosure yields significant power savings due to the fact that the queue entries can be clock-gated on an individual basis.

    Modern microprocessor design strives to reduce power consumption for maximum energy efficiency while also increasing instruction throughput and thus performance via a variety of techniques. The specific mechanism used to select and issue instructions in an out-of-order microprocessor has a significant impact on both power consumption and performance. Various iterations of both shifting and non-shifting issue queues have been used in the past to address these concerns, each with their own set of drawbacks. The issue queue structure proposed here seeks to address both of these concerns by reducing power while also improving performance. Figures 1 through 3 can be used as references for this proposal.

    The issue queue described in this proposal can be used by a microprocessor that dispatches instructions in program order, but issues them Out-of-...